diff --git a/litex_boards/community/platforms/de10lite.py b/litex_boards/community/platforms/de10lite.py
index 6fd7937..4bd6190 100644
--- a/litex_boards/community/platforms/de10lite.py
+++ b/litex_boards/community/platforms/de10lite.py
@@ -51,7 +51,7 @@ _io = [
 
 
     ("gpio_0", 0,
-        Pins("V10 W10 V9 W9 V8 W8 V7 W7 W6 V5 W5 AA15 AA14 W13 W12 AB13 AB12 Y11 AB11 W11 AB10 AA10 AA9 Y8 AA8 Y7 AA7 Y6 AA6 Y5 AA5 Y4 AB3 Y3 AB2 AA2"),
+        Pins("V9 W9 V8 W8 V7 W7 W6 V5 W5 AA15 AA14 W13 W12 AB13 AB12 Y11 AB11 W11 AB10 AA10 AA9 Y8 AA8 Y7 AA7 Y6 AA6 Y5 AA5 Y4 AB3 Y3 AB2 AA2"),
         IOStandard("3.3-V LVTTL")
     ),
     ("gpio_1", 0,
@@ -101,6 +101,9 @@ class Platform(AlteraPlatform):
 
     def __init__(self):
         AlteraPlatform.__init__(self, "10M50DAF484C7G", _io)
+        self.add_platform_command("set_global_assignment -name FAMILY \"MAX 10\"")
+        self.add_platform_command("set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF")
+        self.add_platform_command("set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE \"SINGLE IMAGE WITH ERAM\"")
 
     def create_programmer(self):
         return USBBlaster()
diff --git a/litex_boards/community/targets/de10lite.py b/litex_boards/community/targets/de10lite.py
index 30765b3..d54cbc3 100755
--- a/litex_boards/community/targets/de10lite.py
+++ b/litex_boards/community/targets/de10lite.py
@@ -11,46 +11,65 @@ from litex_boards.platforms import de10lite
 
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.integration.soc_core import mem_decoder
 
 from litedram.modules import IS42S16320
 from litedram.phy import GENSDRPHY
+from litevideo.terminal.core import Terminal
+
 
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
     def __init__(self, platform):
         self.clock_domains.cd_sys    = ClockDomain()
+        self.clock_domains.cd_vga    = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys_ps = ClockDomain()
         self.clock_domains.cd_por    = ClockDomain(reset_less=True)
 
         # # #
 
+        # main input clock for PLL
+        clk50 = platform.request("clk50")
+
         # power on rst
         rst_n = Signal()
         self.sync.por += rst_n.eq(1)
         self.comb += [
-            self.cd_por.clk.eq(self.cd_sys.clk),
+            self.cd_por.clk.eq(clk50),
             self.cd_sys.rst.eq(~rst_n),
             self.cd_sys_ps.rst.eq(~rst_n)
         ]
 
-        # sys clk / sdram clk
-        clk50 = platform.request("clk50")
-        self.comb += self.cd_sys.clk.eq(clk50)
+        # sys clk / sdram clk from PLL
+        pll_clk_out = Signal(6)
+
+        self.comb += self.cd_sys.clk.eq(pll_clk_out[0])
+        self.comb += self.cd_sys_ps.clk.eq(pll_clk_out[1])
+        self.comb += self.cd_vga.clk.eq(pll_clk_out[2])
+
         self.specials += \
             Instance("ALTPLL",
                 p_BANDWIDTH_TYPE         = "AUTO",
                 p_CLK0_DIVIDE_BY         = 1,
                 p_CLK0_DUTY_CYCLE        = 50,
                 p_CLK0_MULTIPLY_BY       = 1,
-                p_CLK0_PHASE_SHIFT       = "-10000",
+                p_CLK0_PHASE_SHIFT       = "0",
+                p_CLK1_DIVIDE_BY         = 1,
+                p_CLK1_DUTY_CYCLE        = 50,
+                p_CLK1_MULTIPLY_BY       = 1,
+                p_CLK1_PHASE_SHIFT       = "-10000",
+                p_CLK2_DIVIDE_BY         = 2,
+                p_CLK2_DUTY_CYCLE        = 50,
+                p_CLK2_MULTIPLY_BY       = 1,
+                p_CLK2_PHASE_SHIFT       = "0",
                 p_COMPENSATE_CLOCK       = "CLK0",
                 p_INCLK0_INPUT_FREQUENCY = 20000,
                 p_INTENDED_DEVICE_FAMILY = "MAX 10",
-                p_LPM_TYPE               =  "altpll",
-                p_OPERATION_MODE         =  "NORMAL",
+                p_LPM_TYPE               = "altpll",
+                p_OPERATION_MODE         = "NORMAL",
                 i_INCLK                  = clk50,
-                o_CLK                    = self.cd_sys_ps.clk,
+                o_CLK                    = pll_clk_out,
                 i_ARESET                 = ~rst_n,
                 i_CLKENA                 = 0x3f,
                 i_EXTCLKENA              = 0xf,
@@ -83,15 +102,44 @@ class BaseSoC(SoCSDRAM):
                 geom_settings   = sdram_module.geom_settings,
                 timing_settings = sdram_module.timing_settings)
 
+# VideoSoC ------------------------------------------------------------------------------------------
+
+class VideoSoC(BaseSoC):
+    mem_map = {
+        "terminal": 0x30000000,
+    }
+    mem_map.update(BaseSoC.mem_map)
+
+    def __init__(self, **kwargs):
+        BaseSoC.__init__(self, **kwargs)
+
+        # create VGA terminal
+        self.submodules.terminal = terminal = Terminal()
+        self.add_wb_slave(mem_decoder(self.mem_map["terminal"]), self.terminal.bus)
+        self.add_memory_region("terminal", self.mem_map["terminal"], 0x10000)
+
+        # connect VGA pins
+        vga = self.platform.request('vga_out', 0)
+        self.comb += [
+            vga.vsync_n.eq(terminal.vsync),
+            vga.hsync_n.eq(terminal.hsync),
+            vga.r.eq(terminal.red[4:8]),
+            vga.g.eq(terminal.green[4:8]),
+            vga.b.eq(terminal.blue[4:8])
+        ]
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Lite")
     builder_args(parser)
     soc_sdram_args(parser)
+    parser.add_argument("--with-vga", action="store_true",
+                        help="enable VGA support")
     args = parser.parse_args()
 
-    soc = BaseSoC(**soc_sdram_argdict(args))
+    cls = VideoSoC if args.with_vga else BaseSoC
+    soc = cls(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()