diff --git a/litex_boards/platforms/sipeed_tang_primer_20k.py b/litex_boards/platforms/sipeed_tang_primer_20k.py
index 9bc7443..6bab707 100644
--- a/litex_boards/platforms/sipeed_tang_primer_20k.py
+++ b/litex_boards/platforms/sipeed_tang_primer_20k.py
@@ -135,10 +135,10 @@ _connectors = [
 
 _dock_io = [
     # Leds
-    ("led", 0,  Pins( "CARD1:44"), IOStandard("LVCMOS33")),
-    ("led", 1,  Pins( "CARD1:46"), IOStandard("LVCMOS33")),
-    ("led", 3,  Pins( "CARD1:40"), IOStandard("LVCMOS33")),
-    ("led", 2,  Pins( "CARD1:42"), IOStandard("LVCMOS33")),
+    ("led", 0,  Pins( "CARD1:44"), IOStandard("LVCMOS18")),
+    ("led", 1,  Pins( "CARD1:46"), IOStandard("LVCMOS18")),
+    ("led", 3,  Pins( "CARD1:40"), IOStandard("LVCMOS18")),
+    ("led", 2,  Pins( "CARD1:42"), IOStandard("LVCMOS18")),
     ("led", 4,  Pins( "CARD1:98"), IOStandard("LVCMOS33")),
     ("led", 5,  Pins("CARD1:136"), IOStandard("LVCMOS33")),
 
@@ -154,14 +154,14 @@ _dock_io = [
 
     # HDMI.
     ("hdmi", 0,
-        Subsignal("clk_p",   Pins("CARD1:132")),
-        Subsignal("clk_n",   Pins("CARD1:130")),
-        Subsignal("data0_p", Pins("CARD1:50")), # Inverted.
-        Subsignal("data0_n", Pins("CARD1:52")),
-        Subsignal("data1_p", Pins("CARD1:62")), # Inverted.
-        Subsignal("data1_n", Pins("CARD1:64")),
-        Subsignal("data2_p", Pins("CARD1:68")), # Inverted.
-        Subsignal("data2_n", Pins("CARD1:70")),
+        Subsignal("clk_p",   Pins("CARD1:68")),
+        Subsignal("clk_n",   Pins("CARD1:70")),
+        Subsignal("data0_p", Pins("CARD1:64")),
+        Subsignal("data0_n", Pins("CARD1:62")),
+        Subsignal("data1_p", Pins("CARD1:58")),
+        Subsignal("data1_n", Pins("CARD1:56")),
+        Subsignal("data2_p", Pins("CARD1:52")),
+        Subsignal("data2_n", Pins("CARD1:50")),
         Subsignal("hdp", Pins("CARD1:154"), IOStandard("LVCMOS18")),
         Subsignal("cec", Pins("CARD1:152"), IOStandard("LVCMOS18")),
         Subsignal("sda", Pins("CARD1:95"),  IOStandard("LVCMOS18")),
diff --git a/litex_boards/targets/sipeed_tang_primer_20k.py b/litex_boards/targets/sipeed_tang_primer_20k.py
index 52ac54c..f478b32 100755
--- a/litex_boards/targets/sipeed_tang_primer_20k.py
+++ b/litex_boards/targets/sipeed_tang_primer_20k.py
@@ -122,7 +122,7 @@ class BaseSoC(SoCCore):
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Primer 20K", **kwargs)
 
         # DDR3 SDRAM -------------------------------------------------------------------------------
-        # FIXME: WIP.
+        # FIXME: WIP / Untested.
         if not self.integrated_main_ram_size:
             self.ddrphy = GW2DDRPHY(
                 pads         = PHYPadsReducer(platform.request("ddram"), [0, 1]),
@@ -176,12 +176,11 @@ class BaseSoC(SoCCore):
 
         # Video ------------------------------------------------------------------------------------
         if with_video_terminal:
-            # FIXME: Un-tested.
             hdmi_pads = platform.request("hdmi")
             self.comb += hdmi_pads.hdp.eq(1)
             self.videophy = VideoHDMIPHY(hdmi_pads, clock_domain="hdmi", pn_swap=["r", "g", "b"])
-            self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
-            #self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
+            #self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
+            self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser: