From 9e9fc5ef78070bf2f08c7e4ea2e085fb0cf1c473 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 9 Jan 2020 19:28:50 +0100 Subject: [PATCH] platforms: always use 1e9/clk_freq for default_clk_period --- litex_boards/partner/platforms/aller.py | 2 +- litex_boards/partner/platforms/nereid.py | 2 +- litex_boards/partner/platforms/orangecrab.py | 2 +- litex_boards/partner/platforms/tagus.py | 2 +- litex_boards/partner/platforms/trellisboard.py | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/litex_boards/partner/platforms/aller.py b/litex_boards/partner/platforms/aller.py index 9315044..4e0fb62 100644 --- a/litex_boards/partner/platforms/aller.py +++ b/litex_boards/partner/platforms/aller.py @@ -105,7 +105,7 @@ _io = [ class Platform(XilinxPlatform): default_clk_name = "clk100" - default_clk_period = 10.0 + default_clk_period = 1e9/100e6 def __init__(self): XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain="vivado") diff --git a/litex_boards/partner/platforms/nereid.py b/litex_boards/partner/platforms/nereid.py index 53299f6..0494c4c 100644 --- a/litex_boards/partner/platforms/nereid.py +++ b/litex_boards/partner/platforms/nereid.py @@ -380,7 +380,7 @@ _connectors = [ class Platform(XilinxPlatform): default_clk_name = "clk100" - default_clk_period = 10.0 + default_clk_period = 1e9/100e6 def __init__(self, toolchain="vivado", programmer="xc3sprog"): XilinxPlatform.__init__(self, "xc7k160t-fbg676-1", _io, _connectors, diff --git a/litex_boards/partner/platforms/orangecrab.py b/litex_boards/partner/platforms/orangecrab.py index 53b36e8..f2c6b09 100644 --- a/litex_boards/partner/platforms/orangecrab.py +++ b/litex_boards/partner/platforms/orangecrab.py @@ -56,7 +56,7 @@ _io = [ class Platform(LatticePlatform): default_clk_name = "clk48" - default_clk_period = int(1e9/48e6) + default_clk_period = 1e9/48e6 def __init__(self, **kwargs): LatticePlatform.__init__(self, "LFE5U-25F-8MG285C", _io, **kwargs) diff --git a/litex_boards/partner/platforms/tagus.py b/litex_boards/partner/platforms/tagus.py index 5e0e658..2c17341 100644 --- a/litex_boards/partner/platforms/tagus.py +++ b/litex_boards/partner/platforms/tagus.py @@ -153,7 +153,7 @@ _connectors = [ class Platform(XilinxPlatform): default_clk_name = "clk100" - default_clk_period = 10.0 + default_clk_period = 1e9/100e6 def __init__(self): XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, _connectors, toolchain="vivado") diff --git a/litex_boards/partner/platforms/trellisboard.py b/litex_boards/partner/platforms/trellisboard.py index df74712..99ce16d 100644 --- a/litex_boards/partner/platforms/trellisboard.py +++ b/litex_boards/partner/platforms/trellisboard.py @@ -204,7 +204,7 @@ _connectors = [ class Platform(LatticePlatform): default_clk_name = "clk12" - default_clk_period = 83 + default_clk_period = 1e9/12e6 def __init__(self, **kwargs): LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG756C", _io, _connectors, **kwargs)