From 9f11bfb0d1f7a6a03b9632da4033f48c3adbef09 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 12 Nov 2020 14:33:45 +0100
Subject: [PATCH] qmtech_ep4ce15: convert name to lowercase, minor cleanup and
 add to test_targets.

---
 .../platforms/{qmtech_EP4CE15.py => qmtech_ep4ce15.py} |  0
 .../targets/{qmtech_EP4CE15.py => qmtech_ep4ce15.py}   | 10 +++++-----
 test/test_targets.py                                   |  1 +
 3 files changed, 6 insertions(+), 5 deletions(-)
 rename litex_boards/platforms/{qmtech_EP4CE15.py => qmtech_ep4ce15.py} (100%)
 rename litex_boards/targets/{qmtech_EP4CE15.py => qmtech_ep4ce15.py} (93%)

diff --git a/litex_boards/platforms/qmtech_EP4CE15.py b/litex_boards/platforms/qmtech_ep4ce15.py
similarity index 100%
rename from litex_boards/platforms/qmtech_EP4CE15.py
rename to litex_boards/platforms/qmtech_ep4ce15.py
diff --git a/litex_boards/targets/qmtech_EP4CE15.py b/litex_boards/targets/qmtech_ep4ce15.py
similarity index 93%
rename from litex_boards/targets/qmtech_EP4CE15.py
rename to litex_boards/targets/qmtech_ep4ce15.py
index b773662..57e498b 100755
--- a/litex_boards/targets/qmtech_EP4CE15.py
+++ b/litex_boards/targets/qmtech_ep4ce15.py
@@ -14,7 +14,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex.build.io import DDROutput
 
-from litex_boards.platforms import qmtech_EP4CE15
+from litex_boards.platforms import qmtech_ep4ce15
 
 from litex.soc.cores.clock import CycloneIVPLL
 from litex.soc.integration.soc_core import *
@@ -61,11 +61,11 @@ class _CRG(Module):
 
 class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(50e6), sdram_rate="1:1", **kwargs):
-        platform = qmtech_EP4CE15.Platform()
+        platform = qmtech_ep4ce15.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
-            ident          = "LiteX SoC on qmtech_EP4CE15",
+            ident          = "LiteX SoC on QMTECH EP4CE15",
             ident_version  = True,
             **kwargs)
 
@@ -95,10 +95,10 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    parser = argparse.ArgumentParser(description="LiteX SoC on qmtech_EP4CE15")
+    parser = argparse.ArgumentParser(description="LiteX SoC on QMTECH EP4CE15")
     parser.add_argument("--build", action="store_true", help="Build bitstream")
     parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--sdram-rate",  default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
+    parser.add_argument("--sdram-rate",  default="1:1", help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate")
     builder_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()
diff --git a/test/test_targets.py b/test/test_targets.py
index 4a041a2..9fb9da4 100644
--- a/test/test_targets.py
+++ b/test/test_targets.py
@@ -81,6 +81,7 @@ class TestTargets(unittest.TestCase):
         # Intel Cyclone4
         platforms.append("de0nano")
         platforms.append("de2_115")
+        platforms.append("qmtech_ep4ce15")
 
         # Intel Cyclone5
         platforms.append("de1soc")