diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py
index 9459f57..5878b9d 100755
--- a/litex_boards/targets/colorlight_5a_75x.py
+++ b/litex_boards/targets/colorlight_5a_75x.py
@@ -152,9 +152,11 @@ class BaseSoC(SoCCore):
             else:
                 sdram_cls  = M12L16161A
             self.add_sdram("sdram",
-                phy           = self.sdrphy,
-                module        = sdram_cls(sys_clk_freq, sdram_rate),
-                l2_cache_size = kwargs.get("l2_size", 8192)
+                phy                     = self.sdrphy,
+                module                  = sdram_cls(sys_clk_freq, sdram_rate),
+                l2_cache_size           = kwargs.get("l2_size", 8192),
+                l2_cache_full_memory_we = False,
+
             )
 
         # Ethernet / Etherbone ---------------------------------------------------------------------