From 9f5e8d48642593cc543a30c84676d366774cef07 Mon Sep 17 00:00:00 2001 From: David Sawatzke Date: Sun, 8 Aug 2021 14:37:46 +0200 Subject: [PATCH] colorlight_5a_75x: Disable full_memory_we for l2 cache by default Leads to an increase in DP16KD, first noticed in https://github.com/enjoy-digital/liteeth/issues/70. With full_mem_we: ``` Info: DP16KD: 41/ 56 73% ``` Without: ``` Info: DP16KD: 29/ 56 51% ``` --- litex_boards/targets/colorlight_5a_75x.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py index 9459f57..5878b9d 100755 --- a/litex_boards/targets/colorlight_5a_75x.py +++ b/litex_boards/targets/colorlight_5a_75x.py @@ -152,9 +152,11 @@ class BaseSoC(SoCCore): else: sdram_cls = M12L16161A self.add_sdram("sdram", - phy = self.sdrphy, - module = sdram_cls(sys_clk_freq, sdram_rate), - l2_cache_size = kwargs.get("l2_size", 8192) + phy = self.sdrphy, + module = sdram_cls(sys_clk_freq, sdram_rate), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_full_memory_we = False, + ) # Ethernet / Etherbone ---------------------------------------------------------------------