From 9ff90eb9fed02143361098dca47e704daa39b8d6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 12 Jan 2021 16:15:52 +0100 Subject: [PATCH] targets/c10lprefkit: fix default sys-clk-freq. --- litex_boards/targets/c10lprefkit.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py index 2f8381e..5259ec8 100755 --- a/litex_boards/targets/c10lprefkit.py +++ b/litex_boards/targets/c10lprefkit.py @@ -109,7 +109,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on C10 LP RefKit") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--sys-clk-freq", default=500e6, help="System clock frequency (default: 50MHz)") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") builder_args(parser) soc_sdram_args(parser)