From a02855d105a629c30ea9ce3501653c1b9eaa1ebc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 2 Jul 2021 15:07:13 +0200 Subject: [PATCH] decklink_quad_hdmi_recorder: Increase sys_clk to 200MHz. --- litex_boards/targets/decklink_quad_hdmi_recorder.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/decklink_quad_hdmi_recorder.py b/litex_boards/targets/decklink_quad_hdmi_recorder.py index 57b73e7..946df46 100755 --- a/litex_boards/targets/decklink_quad_hdmi_recorder.py +++ b/litex_boards/targets/decklink_quad_hdmi_recorder.py @@ -58,7 +58,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs): + def __init__(self, sys_clk_freq=int(200e6), with_pcie=False, **kwargs): platform = quad_hdmi_recorder.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -104,7 +104,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Blackmagic Decklink Quad HDMI Recorder") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") + parser.add_argument("--sys-clk-freq", default=200e6, help="System clock frequency (default: 200MHz)") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") builder_args(parser)