From 68bfb325a59fbbc40a707403d1df8bc2829221bc Mon Sep 17 00:00:00 2001
From: offNaria <yamada@arch.cs.titech.ac.jp>
Date: Mon, 24 Apr 2023 17:35:58 +0900
Subject: [PATCH] Fix Memory test failure of Alveo U250

---
 litex_boards/targets/xilinx_alveo_u250.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/litex_boards/targets/xilinx_alveo_u250.py b/litex_boards/targets/xilinx_alveo_u250.py
index 247e32b..b5d457d 100755
--- a/litex_boards/targets/xilinx_alveo_u250.py
+++ b/litex_boards/targets/xilinx_alveo_u250.py
@@ -74,6 +74,7 @@ class BaseSoC(SoCCore):
             self.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
                 memtype          = "DDR4",
                 sys_clk_freq     = sys_clk_freq,
+                cmd_latency      = 1,
                 iodelay_clk_freq = 500e6,
                 is_rdimm         = True)
             self.add_sdram("sdram",