From a12faae0fbfa4fad68770ec15aa65bce27e3e29b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 14 Apr 2020 11:24:16 +0200 Subject: [PATCH] targets/colorlight_5a_75b: increase sys_ps phase (fixes memtest). --- litex_boards/targets/colorlight_5a_75b.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/colorlight_5a_75b.py b/litex_boards/targets/colorlight_5a_75b.py index 191d2dc..da89d8f 100755 --- a/litex_boards/targets/colorlight_5a_75b.py +++ b/litex_boards/targets/colorlight_5a_75b.py @@ -64,7 +64,7 @@ class _CRG(Module): pll.register_clkin(clk25, 25e6) pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) # Idealy 90° but needs to be increased. self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | ~rst_n) # SDRAM clock @@ -86,7 +86,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.add_sdram("sdram", phy = self.sdrphy, module = M12L16161A(sys_clk_freq, "1:1"),