diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py index 665d18a..70ab772 100755 --- a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py +++ b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py @@ -24,7 +24,7 @@ from litedram.modules import MTA18ASF2G72PZ from litedram.phy.s7ddrphy import K7DDRPHY from liteeth.phy import LiteEthS7PHYRGMII -from litehyperbus.core.hyperbus import HyperRAM +from litex.soc.cores.hyperbus import HyperRAM # CRG ---------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/antmicro_lpddr4_test_board.py b/litex_boards/targets/antmicro_lpddr4_test_board.py index 7740da5..c7ee03e 100755 --- a/litex_boards/targets/antmicro_lpddr4_test_board.py +++ b/litex_boards/targets/antmicro_lpddr4_test_board.py @@ -23,7 +23,7 @@ from litedram.modules import MT53E256M16D1 from litedram.phy import lpddr4 from liteeth.phy import LiteEthS7PHYRGMII -from litehyperbus.core.hyperbus import HyperRAM +from litex.soc.cores.hyperbus import HyperRAM # CRG ---------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py index c12f027..a823011 100755 --- a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py +++ b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py @@ -20,7 +20,7 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.integration.soc import SoCRegion -from litehyperbus.core.hyperbus import HyperRAM +from litex.soc.cores.hyperbus import HyperRAM # CRG ---------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/lattice_crosslink_nx_vip.py b/litex_boards/targets/lattice_crosslink_nx_vip.py index f466e98..3dfa7b0 100755 --- a/litex_boards/targets/lattice_crosslink_nx_vip.py +++ b/litex_boards/targets/lattice_crosslink_nx_vip.py @@ -19,7 +19,7 @@ from litex_boards.platforms import crosslink_nx_vip from litex_boards.platforms import crosslink_nx_vip -from litehyperbus.core.hyperbus import HyperRAM +from litex.soc.cores.hyperbus import HyperRAM from litex.soc.cores.ram import NXLRAM from litex.build.io import CRG diff --git a/litex_boards/targets/sipeed_tang_nano_4k.py b/litex_boards/targets/sipeed_tang_nano_4k.py index 91cebfa..9f7a064 100755 --- a/litex_boards/targets/sipeed_tang_nano_4k.py +++ b/litex_boards/targets/sipeed_tang_nano_4k.py @@ -21,7 +21,7 @@ from litex.soc.cores.video import * from litex_boards.platforms import tang_nano_4k -from litehyperbus.core.hyperbus import HyperRAM +from litex.soc.cores.hyperbus import HyperRAM kB = 1024 mB = 1024*kB diff --git a/litex_boards/targets/sipeed_tang_nano_9k.py b/litex_boards/targets/sipeed_tang_nano_9k.py index 93e354c..a6aa02d 100755 --- a/litex_boards/targets/sipeed_tang_nano_9k.py +++ b/litex_boards/targets/sipeed_tang_nano_9k.py @@ -21,7 +21,7 @@ from litex.soc.cores.video import * from litex_boards.platforms import tang_nano_9k -from litehyperbus.core.hyperbus import HyperRAM +from litex.soc.cores.hyperbus import HyperRAM kB = 1024 mB = 1024*kB diff --git a/litex_boards/targets/trenz_c10lprefkit.py b/litex_boards/targets/trenz_c10lprefkit.py index da0e2aa..1a34b40 100755 --- a/litex_boards/targets/trenz_c10lprefkit.py +++ b/litex_boards/targets/trenz_c10lprefkit.py @@ -25,7 +25,7 @@ from litedram.phy import GENSDRPHY from liteeth.phy.mii import LiteEthPHYMII -from litehyperbus.core.hyperbus import HyperRAM +from litex.soc.cores.hyperbus import HyperRAM # CRG ---------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/trenz_te0725.py b/litex_boards/targets/trenz_te0725.py index d584922..17dc4ec 100755 --- a/litex_boards/targets/trenz_te0725.py +++ b/litex_boards/targets/trenz_te0725.py @@ -20,7 +20,7 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser -from litehyperbus.core.hyperbus import HyperRAM +from litex.soc.cores.hyperbus import HyperRAM # CRG ----------------------------------------------------------------------------------------------