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xilinx_zc706: Add PCIe Gen2 X4 support (Untested on hardware).

This commit is contained in:
Florent Kermarrec 2024-03-26 21:41:41 +01:00
parent fdd4edbd1a
commit a29532b5d7
1 changed files with 18 additions and 2 deletions
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20
litex_boards/targets/xilinx_zc706.py
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@ -30,6 +30,9 @@ from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
from litepcie.phy.s7pciephy import S7PCIEPHY
from litepcie.software import generate_litepcie_software
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(LiteXModule): class _CRG(LiteXModule):
@ -52,7 +55,7 @@ class _CRG(LiteXModule):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs): def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, with_pcie=False, **kwargs):
platform = xilinx_zc706.Platform() platform = xilinx_zc706.Platform()
kwargs["uart_name"] = "crossover" kwargs["uart_name"] = "crossover"
kwargs["with_jtagbone"] = True kwargs["with_jtagbone"] = True
@ -63,6 +66,13 @@ class BaseSoC(SoCCore):
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU706", **kwargs) SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU706", **kwargs)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
if with_led_chaser: if with_led_chaser:
self.leds = LedChaser( self.leds = LedChaser(
@ -75,9 +85,15 @@ def main():
from litex.build.parser import LiteXArgumentParser from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=xilinx_zc706.Platform, description="LiteX SoC on ZC706.") parser = LiteXArgumentParser(platform=xilinx_zc706.Platform, description="LiteX SoC on ZC706.")
parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.") parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.")
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=args.sys_clk_freq, **parser.soc_argdict) soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq,
with_pcie = args.with_pcie,
**parser.soc_argdict
)
builder = Builder(soc, **parser.builder_argdict) builder = Builder(soc, **parser.builder_argdict)
if args.build: if args.build:
builder.build(**parser.toolchain_argdict) builder.build(**parser.toolchain_argdict)