From a4130556ac0b45387e0f6704b7860896a15c494c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 6 Jan 2022 18:37:42 +0100 Subject: [PATCH] gsd_butterstick: Add optional SYZYGY GPIO (--with-syzygy-gpio) to expose the 32 GPIOs on SYZYGY breakout board. --- litex_boards/platforms/gsd_butterstick.py | 5 ++++ litex_boards/targets/gsd_butterstick.py | 35 ++++++++++++++--------- 2 files changed, 27 insertions(+), 13 deletions(-) diff --git a/litex_boards/platforms/gsd_butterstick.py b/litex_boards/platforms/gsd_butterstick.py index a6d9b33..d801473 100644 --- a/litex_boards/platforms/gsd_butterstick.py +++ b/litex_boards/platforms/gsd_butterstick.py @@ -175,6 +175,11 @@ _connectors_r1_0 = [ ), ] +# SYZYGY ------------------------------------------------------------------------------------------- + +def raw_syzygy_io(syzygy, iostandard="LVCMOS33"): + return [(syzygy, 0, Pins(" ".join([f"{syzygy}:S{i:d}" for i in range(32)])), IOStandard(iostandard))] + # Platform ----------------------------------------------------------------------------------------- class Platform(LatticePlatform): diff --git a/litex_boards/targets/gsd_butterstick.py b/litex_boards/targets/gsd_butterstick.py index 7919bb1..b5ffbb4 100755 --- a/litex_boards/targets/gsd_butterstick.py +++ b/litex_boards/targets/gsd_butterstick.py @@ -27,6 +27,7 @@ from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser +from litex.soc.cores.gpio import GPIOTristate from litedram.modules import MT41K64M16,MT41K128M16,MT41K256M16,MT41K512M16 from litedram.phy import ECP5DDRPHY @@ -86,9 +87,10 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, revision="1.0", device="85F", sdram_device="MT41K64M16", sys_clk_freq=int(60e6), toolchain="trellis", with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", - eth_dynamic_ip=False, - with_spi_flash=False, - with_led_chaser=True, + eth_dynamic_ip = False, + with_spi_flash = False, + with_led_chaser = True, + with_syzygy_gpio = True, **kwargs) : platform = butterstick.Platform(revision=revision, device=device ,toolchain=toolchain) @@ -147,6 +149,11 @@ class BaseSoC(SoCCore): pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) + # GPIOs ------------------------------------------------------------------------------------ + if with_syzygy_gpio: + platform.add_extension(butterstick.raw_syzygy_io("SYZYGY0")) + self.submodules.gpio = GPIOTristate(platform.request("SYZYGY0")) + # Build -------------------------------------------------------------------------------------------- def main(): @@ -167,6 +174,7 @@ def main(): sdopts = parser.add_mutually_exclusive_group() sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.") + parser.add_argument("--with-syzygy-gpio",action="store_true", help="Enable GPIOs through SYZYGY Breakout on Port-A.") builder_args(parser) soc_core_args(parser) trellis_args(parser) @@ -175,16 +183,17 @@ def main(): assert not (args.with_etherbone and args.eth_dynamic_ip) soc = BaseSoC( - toolchain = args.toolchain, - revision = args.revision, - device = args.device, - sdram_device = args.sdram_device, - sys_clk_freq = int(float(args.sys_clk_freq)), - with_ethernet = args.with_ethernet, - with_etherbone = args.with_etherbone, - eth_ip = args.eth_ip, - eth_dynamic_ip = args.eth_dynamic_ip, - with_spi_flash = args.with_spi_flash, + toolchain = args.toolchain, + revision = args.revision, + device = args.device, + sdram_device = args.sdram_device, + sys_clk_freq = int(float(args.sys_clk_freq)), + with_ethernet = args.with_ethernet, + with_etherbone = args.with_etherbone, + eth_ip = args.eth_ip, + eth_dynamic_ip = args.eth_dynamic_ip, + with_spi_flash = args.with_spi_flash, + with_syzygy_gpio = args.with_syzygy_gpio, **soc_core_argdict(args)) if args.with_spi_sdcard: soc.add_spi_sdcard()