diff --git a/litex_boards/platforms/camlink_4k.py b/litex_boards/platforms/camlink_4k.py index 39ba685..7e4edbd 100644 --- a/litex_boards/platforms/camlink_4k.py +++ b/litex_boards/platforms/camlink_4k.py @@ -65,8 +65,8 @@ class Platform(LatticePlatform): default_clk_name = "clk27" default_clk_period = 1e9/27e6 - def __init__(self, **kwargs): - LatticePlatform.__init__(self, "LFE5U-25F-8BG381C", _io, **kwargs) + def __init__(self, toolchain="trellis", **kwargs): + LatticePlatform.__init__(self, "LFE5U-25F-8BG381C", _io, toolchain=toolchain, **kwargs) def do_finalize(self, fragment): LatticePlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/colorlight_5a_75b.py b/litex_boards/platforms/colorlight_5a_75b.py index 13f2353..c5da559 100644 --- a/litex_boards/platforms/colorlight_5a_75b.py +++ b/litex_boards/platforms/colorlight_5a_75b.py @@ -215,13 +215,13 @@ class Platform(LatticePlatform): default_clk_name = "clk25" default_clk_period = 1e9/25e6 - def __init__(self, revision="7.0"): + def __init__(self, revision="7.0", toolchain="trellis"): assert revision in ["6.1", "7.0"] self.revision = revision device = {"6.1": "LFE5U-25F-6BG381C", "7.0": "LFE5U-25F-6BG256C"}[revision] io = {"6.1": _io_v6_1, "7.0": _io_v7_0}[revision] connectors = {"6.1": _connectors_v6_1, "7.0": _connectors_v7_0}[revision] - LatticePlatform.__init__(self, device, io, connectors=connectors, toolchain="trellis") + LatticePlatform.__init__(self, device, io, connectors=connectors, toolchain=toolchain) def create_programmer(self): return OpenOCDJTAGProgrammer("openocd_colorlight_5a_75b.cfg") diff --git a/litex_boards/platforms/colorlight_5a_75e.py b/litex_boards/platforms/colorlight_5a_75e.py index 0e2b88c..e352c0a 100644 --- a/litex_boards/platforms/colorlight_5a_75e.py +++ b/litex_boards/platforms/colorlight_5a_75e.py @@ -222,13 +222,13 @@ class Platform(LatticePlatform): default_clk_name = "clk25" default_clk_period = 1e9/25e6 - def __init__(self, revision="7.1"): + def __init__(self, revision="7.1", toolchain="trellis"): assert revision in ["6.0", "7.1"] self.revision = revision device = {"6.0": "LFE5U-25F-6BG256C", "7.1": "LFE5U-25F-6BG256C"}[revision] io = {"6.0": _io_v6_0, "7.1": _io_v7_1}[revision] connectors = {"6.0": _connectors_v6_0, "7.1": _connectors_v7_1}[revision] - LatticePlatform.__init__(self, device, io, connectors=connectors, toolchain="trellis") + LatticePlatform.__init__(self, device, io, connectors=connectors, toolchain=toolchain) def create_programmer(self): return OpenOCDJTAGProgrammer("openocd_colorlight_5a_75b.cfg") diff --git a/litex_boards/platforms/ecp5_evn.py b/litex_boards/platforms/ecp5_evn.py index 8e424e3..1a96862 100644 --- a/litex_boards/platforms/ecp5_evn.py +++ b/litex_boards/platforms/ecp5_evn.py @@ -136,8 +136,8 @@ class Platform(LatticePlatform): default_clk_name = "clk12" default_clk_period = 1e9/12e6 - def __init__(self, **kwargs): - LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG381", _io, _connectors, **kwargs) + def __init__(self, toolchain="trellis", **kwargs): + LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG381", _io, _connectors, toolchain=toolchain, **kwargs) def request(self, *args, **kwargs): import time diff --git a/litex_boards/platforms/ecpix5.py b/litex_boards/platforms/ecpix5.py index c1fd699..56fd519 100644 --- a/litex_boards/platforms/ecpix5.py +++ b/litex_boards/platforms/ecpix5.py @@ -111,8 +111,8 @@ class Platform(LatticePlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self, **kwargs): - LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG554I", _io, _connectors, **kwargs) + def __init__(self, toolchain="trellis", **kwargs): + LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG554I", _io, _connectors, toolchain=toolchain, **kwargs) def create_programmer(self): return OpenOCDJTAGProgrammer("openocd_ecpix5.cfg") diff --git a/litex_boards/platforms/fomu_evt.py b/litex_boards/platforms/fomu_evt.py index 7c4be02..41a8fe9 100644 --- a/litex_boards/platforms/fomu_evt.py +++ b/litex_boards/platforms/fomu_evt.py @@ -86,8 +86,8 @@ class Platform(LatticePlatform): default_clk_name = "clk48" default_clk_period = 1e9/48e6 - def __init__(self): - LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain="icestorm") + def __init__(self, toolchain="icestorm"): + LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain=toolchain) def create_programmer(self): return IceStormProgrammer() diff --git a/litex_boards/platforms/fomu_hacker.py b/litex_boards/platforms/fomu_hacker.py index 37ae8a6..b29e0a2 100644 --- a/litex_boards/platforms/fomu_hacker.py +++ b/litex_boards/platforms/fomu_hacker.py @@ -66,8 +66,8 @@ class Platform(LatticePlatform): default_clk_name = "clk48" default_clk_period = 1e9/48e6 - def __init__(self): - LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io, _connectors, toolchain="icestorm") + def __init__(self, toolchain="icestorm"): + LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io, _connectors, toolchain=toolchain) def create_programmer(self): return IceStormProgrammer() diff --git a/litex_boards/platforms/fomu_pvt.py b/litex_boards/platforms/fomu_pvt.py index 4ccc8dc..39d060e 100644 --- a/litex_boards/platforms/fomu_pvt.py +++ b/litex_boards/platforms/fomu_pvt.py @@ -69,8 +69,8 @@ class Platform(LatticePlatform): default_clk_name = "clk48" default_clk_period = 1e9/48e6 - def __init__(self): - LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io, _connectors, toolchain="icestorm") + def __init__(self, toolchain="icestorm"): + LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io, _connectors, toolchain=toolchain) def create_programmer(self): return IceStormProgrammer() diff --git a/litex_boards/platforms/icebreaker.py b/litex_boards/platforms/icebreaker.py index a998c13..94d36e9 100644 --- a/litex_boards/platforms/icebreaker.py +++ b/litex_boards/platforms/icebreaker.py @@ -89,8 +89,8 @@ class Platform(LatticePlatform): default_clk_name = "clk12" default_clk_period = 1e9/12e6 - def __init__(self): - LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain="icestorm") + def __init__(self, toolchain="icestorm"): + LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain=toolchain) def create_programmer(self): return IceStormProgrammer() diff --git a/litex_boards/platforms/logicbone.py b/litex_boards/platforms/logicbone.py index 4cd0470..5784429 100644 --- a/litex_boards/platforms/logicbone.py +++ b/litex_boards/platforms/logicbone.py @@ -192,12 +192,12 @@ class Platform(LatticePlatform): default_clk_name = "clk25" default_clk_period = 1e9/25e6 - def __init__(self, revision="rev0", device="45F", **kwargs): + def __init__(self, revision="rev0", device="45F", toolchain="trellis", **kwargs): assert revision in ["rev0"] self.revision = revision io = {"rev0": _io_rev0 }[revision] connectors = {"rev0": _connectors_rev0 }[revision] - LatticePlatform.__init__(self, f"LFE5UM5G-{device}-8BG381C", io, connectors, **kwargs) + LatticePlatform.__init__(self, f"LFE5UM5G-{device}-8BG381C", io, connectors, toolchain="trellis", **kwargs) def create_programmer(self): return DFUProg(vid="1d50", pid="6130") diff --git a/litex_boards/platforms/orangecrab.py b/litex_boards/platforms/orangecrab.py index 03a4a46..9d4cab2 100644 --- a/litex_boards/platforms/orangecrab.py +++ b/litex_boards/platforms/orangecrab.py @@ -220,12 +220,12 @@ class Platform(LatticePlatform): default_clk_name = "clk48" default_clk_period = 1e9/48e6 - def __init__(self, revision="0.2", device="25F", **kwargs): + def __init__(self, revision="0.2", device="25F", toolchain="trellis", **kwargs): assert revision in ["0.1", "0.2"] self.revision = revision io = {"0.1": _io_r0_1, "0.2": _io_r0_2 }[revision] connectors = {"0.1": _connectors_r0_1, "0.2": _connectors_r0_2}[revision] - LatticePlatform.__init__(self, f"LFE5U-{device}-8MG285C", io, connectors, **kwargs) + LatticePlatform.__init__(self, f"LFE5U-{device}-8MG285C", io, connectors, toolchain=toolchain, **kwargs) def create_programmer(self): return DFUProg(vid="1209", pid="5af0") diff --git a/litex_boards/platforms/tinyfpga_bx.py b/litex_boards/platforms/tinyfpga_bx.py index 347cd86..da0aaf1 100644 --- a/litex_boards/platforms/tinyfpga_bx.py +++ b/litex_boards/platforms/tinyfpga_bx.py @@ -67,8 +67,8 @@ class Platform(LatticePlatform): default_clk_name = "clk16" default_clk_period = 1e9/16e6 - def __init__(self): - LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors, toolchain="icestorm") + def __init__(self, toolchain="icestorm"): + LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors, toolchain=toolchain) self.add_extension(serial) def create_programmer(self): diff --git a/litex_boards/platforms/trellisboard.py b/litex_boards/platforms/trellisboard.py index fd35511..3021b54 100644 --- a/litex_boards/platforms/trellisboard.py +++ b/litex_boards/platforms/trellisboard.py @@ -259,8 +259,8 @@ class Platform(LatticePlatform): default_clk_name = "clk12" default_clk_period = 1e9/12e6 - def __init__(self, **kwargs): - LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG756C", _io, _connectors, **kwargs) + def __init__(self, toolchain="trellis", **kwargs): + LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG756C", _io, _connectors, toolchain=toolchain, **kwargs) def create_programmer(self): return OpenOCDJTAGProgrammer("openocd_trellisboard.cfg") diff --git a/litex_boards/platforms/ulx3s.py b/litex_boards/platforms/ulx3s.py index f360259..fc455b7 100644 --- a/litex_boards/platforms/ulx3s.py +++ b/litex_boards/platforms/ulx3s.py @@ -146,11 +146,11 @@ class Platform(LatticePlatform): default_clk_name = "clk25" default_clk_period = 1e9/25e6 - def __init__(self, device="LFE5U-45F", revision="2.0", **kwargs): + def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis", **kwargs): assert device in ["LFE5U-12F", "LFE5U-25F", "LFE5U-45F", "LFE5U-85F"] assert revision in ["1.7", "2.0"] _io = _io_common + {"1.7": _io_1_7, "2.0": _io_2_0}[revision] - LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs) + LatticePlatform.__init__(self, device + "-6BG381C", _io, toolchain=toolchain, **kwargs) def create_programmer(self): return UJProg() diff --git a/litex_boards/platforms/versa_ecp5.py b/litex_boards/platforms/versa_ecp5.py index 41021e0..f8dd49a 100644 --- a/litex_boards/platforms/versa_ecp5.py +++ b/litex_boards/platforms/versa_ecp5.py @@ -235,9 +235,9 @@ class Platform(LatticePlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self, device="LFE5UM5G", **kwargs): + def __init__(self, device="LFE5UM5G", toolchain="trellis", **kwargs): assert device in ["LFE5UM5G", "LFE5UM"] - LatticePlatform.__init__(self, device + "-45F-8BG381C", _io, _connectors, **kwargs) + LatticePlatform.__init__(self, device + "-45F-8BG381C", _io, _connectors, toolchain=toolchain, **kwargs) def create_programmer(self): return OpenOCDJTAGProgrammer("openocd_versa_ecp5.cfg")