From 1f65d37121c2171d52e7dfc7801eac558130ef95 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 15 Oct 2021 16:44:35 +0200 Subject: [PATCH] Enable writing to flash for T20 --- litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py index 037ea0c..2a70d94 100755 --- a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py @@ -86,6 +86,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--flash", action="store_true", help="Flash bitstream") parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)") builder_args(parser) @@ -103,5 +104,10 @@ def main(): prog = soc.platform.create_programmer() prog.load_bitstream(os.path.join(builder.gateware_dir, f"outflow/{soc.build_name}.bit")) + if args.flash: + from litex.build.openfpgaloader import OpenFPGALoader + prog = OpenFPGALoader("trion_t120_bga576") + prog.flash(0, os.path.join(builder.gateware_dir, f"outflow/{soc.build_name}.hex")) + if __name__ == "__main__": main()