diff --git a/litex_boards/platforms/digilent_cmod_a7.py b/litex_boards/platforms/digilent_cmod_a7.py
index 521eaaa..56976d8 100644
--- a/litex_boards/platforms/digilent_cmod_a7.py
+++ b/litex_boards/platforms/digilent_cmod_a7.py
@@ -49,6 +49,7 @@ _io = [
             IOStandard("LVCMOS33")),
         Subsignal("wen", Pins("R19"), IOStandard("LVCMOS33")),
         Subsignal("cen", Pins("N19"), IOStandard("LVCMOS33")),
+        Subsignal("oe",  Pins("P19"), IOStandard("LVCMOS33")),
         Misc("SLEW=FAST"),
     ),
 
diff --git a/litex_boards/targets/digilent_cmod_a7.py b/litex_boards/targets/digilent_cmod_a7.py
index 291b22f..3216e17 100755
--- a/litex_boards/targets/digilent_cmod_a7.py
+++ b/litex_boards/targets/digilent_cmod_a7.py
@@ -70,7 +70,8 @@ class AsyncSRAM(LiteXModule):
         self.comb += [
             cen.eq(~chip_ena),
             wen.eq(~write_ena),
-            tristate_data.oe.eq(write_ena)
+            tristate_data.oe.eq(write_ena),
+            oe.eq(tristate_data.oe),
         ]
         ########################
         # address and data