target/efinix_ti60_f225: Add L2 Cache (16KB for now) to improve perfs/Coremark.

This commit is contained in:
Florent Kermarrec 2024-04-23 11:45:07 +02:00
parent e4a15f6064
commit a6b8457111
1 changed files with 23 additions and 2 deletions

View File

@ -17,6 +17,7 @@ from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.integration.soc import SoCRegion from litex.soc.integration.soc import SoCRegion
from litex.soc.interconnect import wishbone
from litex.soc.cores.hyperbus import HyperRAM from litex.soc.cores.hyperbus import HyperRAM
@ -72,8 +73,28 @@ class BaseSoC(SoCCore):
# HyperRAM --------------------------------------------------------------------------------- # HyperRAM ---------------------------------------------------------------------------------
if with_hyperram: if with_hyperram:
self.hyperram = HyperRAM(platform.request("hyperram"), latency=7, sys_clk_freq=sys_clk_freq) # HyperRAM Parameters.
self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=32*1024*1024)) hyperram_device = "W958D6NW"
hyperram_size = 32*1024*1024
hyperram_cache_size = 16*1024
# HyperRAM Bus/Slave Interface.
hyperram_bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
self.bus.add_slave(name="main_ram", slave=hyperram_bus, region=SoCRegion(origin=0x40000000, size=hyperram_size))
# HyperRAM L2 Cache.
hyperram_cache = wishbone.Cache(
cachesize = hyperram_cache_size//4,
master = hyperram_bus,
slave = wishbone.Interface(data_width=32, address_width=32, addressing="word")
)
hyperram_cache = FullMemoryWE()(hyperram_cache)
self.hyperram_cache = hyperram_cache
self.add_config("L2_SIZE", hyperram_cache_size)
# HyperRAM Core.
self.hyperram = HyperRAM(platform.request("hyperram"), latency=7, latency_mode="variable", sys_clk_freq=sys_clk_freq)
self.comb += self.hyperram_cache.slave.connect(self.hyperram.bus)
# Ethernet / Etherbone --------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone: if with_ethernet or with_etherbone: