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target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally

This commit is contained in:
Gwenhael Goavec-Merou 2023-10-23 17:16:57 +02:00
parent 16319f5cf0
commit a6f3c5276e
26 changed files with 21 additions and 148 deletions
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5
litex_boards/targets/adi_adrv2crr_fmc.py
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@ -71,6 +71,8 @@ class BaseSoC(SoCCore):
self.crg = CRG(platform, sys_clk_freq, ddram_channel)
# SoCCore ----------------------------------------------------------------------------------
kwargs["with_jtagbone"] = True
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ADI ADRV2CRR-FMC", **kwargs)
# DDR4 SDRAM -------------------------------------------------------------------------------
@ -117,9 +119,6 @@ class BaseSoC(SoCCore):
# SYSMON -----------------------------------------------------------------------------------
self.sysmon = ZynqUSPSystemMonitor()
# JTAG -------------------------------------------------------------------------------------
self.add_jtagbone()
# Build --------------------------------------------------------------------------------------------
def main():

6
litex_boards/targets/adi_plutosdr.py
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@ -64,12 +64,10 @@ class BaseSoC(SoCCore):
self.crg = _CRG(platform, sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
kwargs["uart_name"] = "crossover"
kwargs["uart_name"] = "crossover"
kwargs["with_jtagbone"] = True
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Pluto SDR", **kwargs)
# JTAGBone ---------------------------------------------------------------------------------
self.add_jtagbone()
# GPIOS ------------------------------------------------------------------------------------
self.comb += platform.request("gpio", 0).eq(ClockSignal("sys"))

3
litex_boards/targets/analog_pocket.py
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@ -144,9 +144,6 @@ class BaseSoC(SoCCore):
# litex_term crossover
# litescope_cli -r main_vfb_dma_source_source_last
# Add JTAGBone.
self.add_jtagbone()
# Add UART auto-flush.
self.uart.add_auto_tx_flush(sys_clk_freq=sys_clk_freq, timeout=1, interval=128)

3
litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
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@ -85,7 +85,6 @@ class BaseSoC(SoCCore):
eth_dynamic_ip = False,
with_hyperram = False,
with_sdcard = False,
with_jtagbone = True,
with_uartbone = False,
with_spi_flash = False,
with_led_chaser = True,
@ -205,7 +204,6 @@ def main():
parser.add_target_argument("--eth-reset-time", default="10e-3", help="Duration of Ethernet PHY reset.")
parser.add_target_argument("--with-hyperram", action="store_true", help="Add HyperRAM.")
parser.add_target_argument("--with-sdcard", action="store_true", help="Add SDCard.")
parser.add_target_argument("--with-jtagbone", action="store_true", help="Add JTAGBone.")
parser.add_target_argument("--with-uartbone", action="store_true", help="Add UartBone on 2nd serial.")
parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
parser.add_target_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
@ -223,7 +221,6 @@ def main():
eth_dynamic_ip = args.eth_dynamic_ip,
with_hyperram = args.with_hyperram,
with_sdcard = args.with_sdcard,
with_jtagbone = args.with_jtagbone,
with_uartbone = args.with_uartbone,
with_spi_flash = args.with_spi_flash,
with_video_terminal = args.with_video_terminal,

7
litex_boards/targets/antmicro_lpddr4_test_board.py
View File

@ -55,7 +55,6 @@ class BaseSoC(SoCCore):
eth_dynamic_ip = False,
with_hyperram = False,
with_sdcard = False,
with_jtagbone = True,
with_uartbone = False,
with_led_chaser = True,
**kwargs):
@ -104,10 +103,6 @@ class BaseSoC(SoCCore):
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# UartBone ---------------------------------------------------------------------------------
if with_uartbone:
self.add_uartbone(baudrate=1e6)
@ -133,7 +128,6 @@ def main():
parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
parser.add_target_argument("--with-hyperram", action="store_true", help="Add HyperRAM.")
parser.add_target_argument("--with-sdcard", action="store_true", help="Add SDCard.")
parser.add_target_argument("--with-jtagbone", action="store_true", help="Add JTAGBone.")
parser.add_target_argument("--with-uartbone", action="store_true", help="Add UartBone on 2nd serial.")
args = parser.parse_args()
@ -148,7 +142,6 @@ def main():
eth_dynamic_ip = args.eth_dynamic_ip,
with_hyperram = args.with_hyperram,
with_sdcard = args.with_sdcard,
with_jtagbone = args.with_jtagbone,
with_uartbone = args.with_uartbone,
**parser.soc_argdict)
builder = Builder(soc, **parser.builder_argdict)

4
litex_boards/targets/arduino_mkrvidor4000.py
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@ -55,9 +55,9 @@ class BaseSoC(SoCCore):
self.crg = _CRG(platform, sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on MKR Vidor 4000", **kwargs)
kwargs["with_jtagbone"] = True # TODO: untested
self.add_jtagbone() # TODO: untested
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on MKR Vidor 4000", **kwargs)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:

7
litex_boards/targets/colorlight_i9plus.py
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@ -84,7 +84,6 @@ class BaseSoC(SoCCore):
eth_ip = "192.168.1.50",
eth_dynamic_ip = False,
with_led_chaser = True,
with_jtagbone = True,
with_spi_flash = False,
**kwargs):
platform = colorlight_i9plus.Platform(toolchain=toolchain)
@ -127,10 +126,6 @@ class BaseSoC(SoCCore):
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import MX25L12833F
@ -160,7 +155,6 @@ def main():
parser.add_target_argument("--eth-port", default=0, type=int, help="Ethernet port to use (0/1)")
parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
args = parser.parse_args()
@ -176,7 +170,6 @@ def main():
eth_port = args.eth_port,
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
with_jtagbone = args.with_jtagbone,
with_spi_flash = args.with_spi_flash,
**parser.soc_argdict
)

6
litex_boards/targets/decklink_quad_hdmi_recorder.py
View File

@ -69,12 +69,10 @@ class BaseSoC(SoCCore):
self.crg = _CRG(platform, sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
kwargs["uart_name"] = "crossover"
kwargs["uart_name"] = "crossover"
kwargs["with_jtabone"] = True
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Blackmagic Decklink Quad HDMI Recorder", **kwargs)
# JTAGBone --------------------------------------------------------------------------------
self.add_jtagbone()
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.ddrphy = usddrphy.USDDRPHY(

7
litex_boards/targets/digilent_arty.py
View File

@ -78,7 +78,6 @@ class BaseSoC(SoCCore):
eth_ip = "192.168.1.50",
eth_dynamic_ip = False,
with_led_chaser = True,
with_jtagbone = True,
with_spi_flash = False,
with_buttons = False,
with_pmod_gpio = False,
@ -123,10 +122,6 @@ class BaseSoC(SoCCore):
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import S25FL128L
@ -174,7 +169,6 @@ def main():
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_target_argument("--sdcard-adapter", help="SDCard PMOD adapter (digilent or numato).")
parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
parser.add_target_argument("--with-pmod-gpio", action="store_true", help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
args = parser.parse_args()
@ -191,7 +185,6 @@ def main():
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
with_jtagbone = args.with_jtagbone,
with_spi_flash = args.with_spi_flash,
with_pmod_gpio = args.with_pmod_gpio,
**parser.soc_argdict

7
litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py
View File

@ -53,7 +53,6 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=200e6,
with_spi_flash = False,
with_hyperram = False,
with_jtagbone = False,
with_ethernet = False,
with_etherbone = False,
eth_phy = 0,
@ -67,10 +66,6 @@ class BaseSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Efinix Titanium Ti60 F225 Dev Kit", **kwargs)
# JTAGBone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q64JW
@ -122,7 +117,6 @@ def main():
parser.add_target_argument("--sys-clk-freq", default=200e6, type=float, help="System clock frequency.")
parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
parser.add_target_argument("--with-hyperram", action="store_true", help="Enable HyperRAM.")
parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
sdopts = parser.target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
@ -137,7 +131,6 @@ def main():
sys_clk_freq = args.sys_clk_freq,
with_spi_flash = args.with_spi_flash,
with_hyperram = args.with_hyperram,
with_jtagbone = args.with_jtagbone,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,

8
litex_boards/targets/isx_im1283.py
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@ -51,7 +51,7 @@ class _CRG(LiteXModule):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=80e6, with_led_chaser=True, with_jtagbone=True, **kwargs):
def __init__(self, sys_clk_freq=80e6, with_led_chaser=True, **kwargs):
platform = isx_im1283.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -62,10 +62,6 @@ class BaseSoC(SoCCore):
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
@ -90,7 +86,6 @@ def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=isx_im1283.Platform, description="LiteX SoC on iM1283.")
parser.add_argument("--sys-clk-freq", default=80e6, type=float, help="System clock frequency.")
parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
@ -98,7 +93,6 @@ def main():
soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq,
with_jtagbone = args.with_jtagbone,
**parser.soc_argdict
)
if args.with_spi_sdcard:

7
litex_boards/targets/lattice_ecp5_evn.py
View File

@ -46,7 +46,6 @@ class _CRG(LiteXModule):
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=50e6, toolchain="trellis", x5_clk_freq=None,
with_led_chaser = True,
with_jtagbone = True,
**kwargs):
platform = lattice_ecp5_evn.Platform(toolchain=toolchain)
@ -56,10 +55,6 @@ class BaseSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ECP5 Evaluation Board", **kwargs)
# JtagBone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
@ -73,14 +68,12 @@ def main():
parser = LiteXArgumentParser(platform=lattice_ecp5_evn.Platform, description="LiteX SoC on ECP5 Evaluation Board.")
parser.add_target_argument("--sys-clk-freq", default=60e6, type=float, help="System clock frequency.")
parser.add_target_argument("--x5-clk-freq", type=int, help="Use X5 oscillator as system clock at the specified frequency.")
parser.add_target_argument("--with-jtagbone", action="store_true", help="Add JTAGBone.")
args = parser.parse_args()
soc = BaseSoC(
toolchain = args.toolchain,
sys_clk_freq = args.sys_clk_freq,
x5_clk_freq = args.x5_clk_freq,
with_jtagbone = args.with_jtagbone,
**parser.soc_argdict)
builder = Builder(soc, **parser.builder_argdict)
if args.build:

6
litex_boards/targets/limesdr_mini_v2.py
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@ -75,12 +75,10 @@ class BaseSoC(SoCCore):
platform = limesdr_mini_v2.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
kwargs["uart_name"] = "crossover"
kwargs["uart_name"] = "crossover"
kwargs["with_jtagbone"] = True
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on LimeSDR-Mini-V2", **kwargs)
# JTAGBone ---------------------------------------------------------------------------------
self.add_jtagbone()
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq)

4
litex_boards/targets/mnt_rkx7.py
View File

@ -94,6 +94,7 @@ class BaseSoC(SoCCore):
self.crg = _CRG(platform, sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
#kwargs["with_jtagbone"] = True
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on MNT-RKX7", **kwargs)
# DDR3 SDRAM -------------------------------------------------------------------------------
@ -142,9 +143,6 @@ class BaseSoC(SoCCore):
self.i2c1 = I2CMaster(platform.request("i2c", 1))
self.i2c2 = I2CMaster(platform.request("i2c", 2))
# JTAG -------------------------------------------------------------------------------------
#self.add_jtagbone()
# Backlight --------------------------------------------------------------------------------
# Motherboard display connector backlight, currently unused (the new backlight signals
# are on the 50pin RGB->eDP connector)

6
litex_boards/targets/newae_cw305.py
View File

@ -65,12 +65,10 @@ class BaseSoC(SoCCore):
self.crg = _CRG(platform, sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
kwargs["uart_name"] = "crossover"
kwargs["uart_name"] = "crossover"
kwargs["with_jtagbone"] = True
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on NewAE-CW305", **kwargs)
# JTAGBone ---------------------------------------------------------------------------------
self.add_jtagbone()
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(

7
litex_boards/targets/qmtech_artix7_fbg484.py
View File

@ -75,7 +75,6 @@ class BaseSoC(SoCCore):
with_led_chaser = True,
with_video_terminal = False,
with_video_framebuffer = False,
with_jtagbone = True,
with_spi_flash = False,
**kwargs):
platform = qmtech_artix7_fbg484.Platform(kgates=kgates, toolchain=toolchain, with_daughterboard=with_daughterboard)
@ -117,10 +116,6 @@ class BaseSoC(SoCCore):
# The daughterboard has the tx clock wired to a non-clock pin, so we can't help it
self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]")
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import MT25QL128
@ -160,7 +155,6 @@ def main():
sdopts = parser.target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
viopts = parser.target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
@ -176,7 +170,6 @@ def main():
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
with_jtagbone = args.with_jtagbone,
with_spi_flash = args.with_spi_flash,
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,

7
litex_boards/targets/qmtech_artix7_fgg676.py
View File

@ -75,7 +75,6 @@ class BaseSoC(SoCCore):
with_led_chaser = True,
with_video_terminal = False,
with_video_framebuffer = False,
with_jtagbone = True,
with_spi_flash = False,
**kwargs):
platform = qmtech_artix7_fgg676.Platform(kgates=kgates, toolchain=toolchain, with_daughterboard=with_daughterboard)
@ -117,10 +116,6 @@ class BaseSoC(SoCCore):
# The daughterboard has the tx clock wired to a non-clock pin, so we can't help it
self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]")
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import MT25QL128
@ -160,7 +155,6 @@ def main():
sdopts = parser.target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
viopts = parser.target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
@ -176,7 +170,6 @@ def main():
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
with_jtagbone = args.with_jtagbone,
with_spi_flash = args.with_spi_flash,
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,

14
litex_boards/targets/qmtech_ep4ce15_starter_kit.py
View File

@ -61,8 +61,6 @@ class _CRG(LiteXModule):
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=50e6,
with_jtaguart = False,
with_jtagbone = False,
with_led_chaser = True,
sdram_rate = "1:1",
**kwargs):
@ -72,20 +70,14 @@ class BaseSoC(SoCCore):
self.crg = _CRG(platform, sys_clk_freq, sdram_rate = sdram_rate)
# SoCCore ----------------------------------------------------------------------------------
if with_jtagbone:
if kwargs["with_jtagbone"]:
kwargs["uart_name"] = "crossover"
if with_jtaguart:
kwargs["uart_name"] = "jtag_uart"
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on QMTECH Cyclone IV Starter Kit",
**kwargs
)
# JTAGbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
@ -111,15 +103,11 @@ def main():
parser = LiteXArgumentParser(platform=qmtech_ep4ce15_starter_kit.Platform, description="LiteX SoC on QMTECH EP4CE15")
parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
parser.add_target_argument("--with-jtaguart", action="store_true", help="Enable JTAGUart support.")
parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq,
sdram_rate = args.sdram_rate,
with_jtagbone = args.with_jtagbone,
with_jtaguart = args.with_jtaguart,
**parser.soc_argdict
)

7
litex_boards/targets/qmtech_xc7a35t.py
View File

@ -75,7 +75,6 @@ class BaseSoC(SoCCore):
with_led_chaser = True,
with_video_terminal = False,
with_video_framebuffer = False,
with_jtagbone = True,
with_spi_flash = False,
**kwargs):
platform = qmtech_xc7a35t.Platform(toolchain=toolchain, with_daughterboard=with_daughterboard)
@ -117,10 +116,6 @@ class BaseSoC(SoCCore):
# The daughterboard has the tx clock wired to a non-clock pin, so we can't help it
self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]")
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import MT25QL128
@ -159,7 +154,6 @@ def main():
sdopts = parser.target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
viopts = parser.target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
@ -174,7 +168,6 @@ def main():
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
with_jtagbone = args.with_jtagbone,
with_spi_flash = args.with_spi_flash,
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,

8
litex_boards/targets/qmtech_xc7k325t.py
View File

@ -69,7 +69,7 @@ class BaseSoC(SoCCore):
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
local_ip="", remote_ip="",
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, with_video_colorbars=False,
with_jtagbone=True, with_spi_flash=False, **kwargs):
with_spi_flash=False, **kwargs):
platform = qmtech_xc7k325t.Platform(toolchain=toolchain, with_daughterboard=with_daughterboard)
# SoCCore ----------------------------------------------------------------------------------
@ -125,10 +125,6 @@ class BaseSoC(SoCCore):
self.add_constant("REMOTEIP3", int(remote_ip[2]))
self.add_constant("REMOTEIP4", int(remote_ip[3]))
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import MT25QL128
@ -182,7 +178,6 @@ def main():
sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
@ -203,7 +198,6 @@ def main():
eth_dynamic_ip = args.eth_dynamic_ip,
local_ip = args.local_ip,
remote_ip = args.remote_ip,
with_jtagbone = args.with_jtagbone,
with_spi_flash = args.with_spi_flash,
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,

7
litex_boards/targets/seeedstudio_spartan_edge_accelerator.py
View File

@ -64,7 +64,6 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=100e6,
with_led_chaser = True,
with_jtagbone = False,
with_video_terminal = True,
with_neopixel = False,
**kwargs):
@ -77,10 +76,6 @@ class BaseSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Seeedstudio Spartan Edge Accelerator", **kwargs)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
@ -108,14 +103,12 @@ def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=seeedstudio_spartan_edge_accelerator.Platform, description="LiteX SoC on Spartan Edge Accelerator.")
parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Colorbars (HDMI).")
parser.add_target_argument("--with-neopixel", action="store_true", help="Enable onboard 2 Neopixels Leds.")
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq,
with_jtagbone = args.with_jtagbone,
with_video_terminal = args.with_video_terminal,
with_neopixel = args.with_neopixel,
**parser.soc_argdict

7
litex_boards/targets/sitlinv_stlv7325_v1.py
View File

@ -80,7 +80,6 @@ class BaseSoC(SoCCore):
with_led_chaser = True,
with_pcie = False,
with_sata = False,
with_jtagbone = True,
with_video_colorbars = False,
with_video_framebuffer = False,
with_video_terminal = False,
@ -106,10 +105,6 @@ class BaseSoC(SoCCore):
l2_cache_size = kwargs.get("l2_size", 8192),
)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.ethphy = LiteEthPHY(
@ -200,7 +195,6 @@ def main():
parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.")
parser.add_target_argument("--with-sata", action="store_true", help="Enable SATA support.")
parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
sdopts = parser.target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
@ -222,7 +216,6 @@ def main():
eth_dynamic_ip = args.eth_dynamic_ip,
with_pcie = args.with_pcie,
with_sata = args.with_sata,
with_jtagbone = args.with_jtagbone,
with_video_colorbars = args.with_video_colorbars,
with_video_framebuffer = args.with_video_framebuffer,
with_video_terminal = args.with_video_terminal,

7
litex_boards/targets/sitlinv_stlv7325_v2.py
View File

@ -77,7 +77,6 @@ class BaseSoC(SoCCore):
with_led_chaser = True,
with_pcie = False,
with_sata = False, sata_gen="gen2",
with_jtagbone = False,
with_video_colorbars = False,
with_video_framebuffer = False,
with_video_terminal = False,
@ -103,10 +102,6 @@ class BaseSoC(SoCCore):
l2_cache_size = kwargs.get("l2_size", 8192),
)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet:
self.ethphy = LiteEthPHYRGMII(
@ -178,7 +173,6 @@ def main():
parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
parser.add_target_argument("--with-sata", action="store_true", help="Enable SATA support.")
parser.add_target_argument("--sata-gen", default="2", help="SATA Gen..", choices=["1", "2", "3"])
parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
sdopts = parser.target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
@ -195,7 +189,6 @@ def main():
with_pcie = args.with_pcie,
with_sata = args.with_sata,
sata_gen = "gen" + args.sata_gen,
with_jtagbone = args.with_jtagbone,
with_video_colorbars = args.with_video_colorbars,
with_video_framebuffer = args.with_video_framebuffer,
with_video_terminal = args.with_video_terminal,

5
litex_boards/targets/sqrl_fk33.py
View File

@ -73,11 +73,10 @@ class BaseSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
if kwargs.get("uart_name", "serial") == "serial":
kwargs["uart_name"] = "crossover" # Defaults to Crossover-UART.
kwargs["with_jtagbone"] = True
kwargs["jtagbone_chain"] = 2 # Chain 1 already used by HBM2 debug probes.
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on FK33", **kwargs)
# JTAGBone --------------------------------------------------------------------------------
self.add_jtagbone(chain=2) # Chain 1 already used by HBM2 debug probes.
# HBM --------------------------------------------------------------------------------------
if with_hbm:
# Add HBM Core.

9
litex_boards/targets/terasic_deca.py
View File

@ -59,7 +59,6 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=50e6,
with_led_chaser = True,
with_uartbone = False,
with_jtagbone = False,
with_video_terminal = False,
with_spi_sdcard = False,
with_ethernet = False,
@ -76,7 +75,7 @@ class BaseSoC(SoCCore):
# Defaults to JTAG-UART since no hardware UART.
real_uart_name = kwargs["uart_name"]
if real_uart_name == "serial":
if with_jtagbone:
if kwargs["with_jtagbone"]:
kwargs["uart_name"] = "crossover"
else:
kwargs["uart_name"] = "jtag_uart"
@ -88,10 +87,6 @@ class BaseSoC(SoCCore):
if with_uartbone:
self.add_uartbone(uart_name=real_uart_name, baudrate=kwargs["uart_baudrate"])
# JTAGbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.platform.toolchain.additional_sdc_commands += [
@ -150,7 +145,6 @@ def main():
parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
parser.add_target_argument("--with-uartbone", action="store_true", help="Enable UARTbone support.")
parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
parser.add_target_argument("--with-spi-sdcard", action="store_true", help="Enable SPI SD card controller.")
args = parser.parse_args()
@ -162,7 +156,6 @@ def main():
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
with_uartbone = args.with_uartbone,
with_jtagbone = args.with_jtagbone,
with_video_terminal = args.with_video_terminal,
with_spi_sdcard = args.with_spi_sdcard,
**parser.soc_argdict

5
litex_boards/targets/xilinx_alveo_u280.py
View File

@ -102,13 +102,12 @@ class BaseSoC(SoCCore):
self.crg = _CRG(platform, sys_clk_freq, ddram_channel, with_hbm)
# SoCCore ----------------------------------------------------------------------------------
kwargs["jtagbone_chain"] = 2 # Chain 1 already used by HBM2 debug probes.
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alveo U280 (ES1)", **kwargs)
# HBM / DRAM -------------------------------------------------------------------------------
if with_hbm:
# JTAGBone -----------------------------------------------------------------------------
#self.add_jtagbone(chain=2) # Chain 1 already used by HBM2 debug probes.
# Add HBM Core.
self.hbm = hbm = ClockDomainsRenamer({"axi": "sys"})(USPHBM2(platform))