diff --git a/litex_boards/targets/adi_adrv2crr_fmc.py b/litex_boards/targets/adi_adrv2crr_fmc.py
index 395142e..5597c61 100755
--- a/litex_boards/targets/adi_adrv2crr_fmc.py
+++ b/litex_boards/targets/adi_adrv2crr_fmc.py
@@ -71,6 +71,8 @@ class BaseSoC(SoCCore):
         self.crg = CRG(platform, sys_clk_freq, ddram_channel)
 
         # SoCCore ----------------------------------------------------------------------------------
+        kwargs["with_jtagbone"] = True
+
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ADI ADRV2CRR-FMC", **kwargs)
 
         # DDR4 SDRAM -------------------------------------------------------------------------------
@@ -117,9 +119,6 @@ class BaseSoC(SoCCore):
         # SYSMON -----------------------------------------------------------------------------------
         self.sysmon = ZynqUSPSystemMonitor()
 
-        # JTAG -------------------------------------------------------------------------------------
-        self.add_jtagbone()
-
 # Build --------------------------------------------------------------------------------------------
 
 def main():
diff --git a/litex_boards/targets/adi_plutosdr.py b/litex_boards/targets/adi_plutosdr.py
index d7f819a..270fa6b 100755
--- a/litex_boards/targets/adi_plutosdr.py
+++ b/litex_boards/targets/adi_plutosdr.py
@@ -64,12 +64,10 @@ class BaseSoC(SoCCore):
         self.crg = _CRG(platform, sys_clk_freq)
 
         # SoCCore ----------------------------------------------------------------------------------
-        kwargs["uart_name"] = "crossover"
+        kwargs["uart_name"]     = "crossover"
+        kwargs["with_jtagbone"] = True
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Pluto SDR", **kwargs)
 
-        # JTAGBone ---------------------------------------------------------------------------------
-        self.add_jtagbone()
-
         # GPIOS ------------------------------------------------------------------------------------
         self.comb += platform.request("gpio", 0).eq(ClockSignal("sys"))
 
diff --git a/litex_boards/targets/analog_pocket.py b/litex_boards/targets/analog_pocket.py
index 4709817..0058082 100755
--- a/litex_boards/targets/analog_pocket.py
+++ b/litex_boards/targets/analog_pocket.py
@@ -144,9 +144,6 @@ class BaseSoC(SoCCore):
                     # litex_term crossover
                     # litescope_cli -r main_vfb_dma_source_source_last
 
-                    # Add JTAGBone.
-                    self.add_jtagbone()
-
                     # Add UART auto-flush.
                     self.uart.add_auto_tx_flush(sys_clk_freq=sys_clk_freq, timeout=1, interval=128)
 
diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
index 0aab059..074dacd 100755
--- a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
+++ b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
@@ -85,7 +85,6 @@ class BaseSoC(SoCCore):
             eth_dynamic_ip         = False,
             with_hyperram          = False,
             with_sdcard            = False,
-            with_jtagbone          = True,
             with_uartbone          = False,
             with_spi_flash         = False,
             with_led_chaser        = True,
@@ -205,7 +204,6 @@ def main():
     parser.add_target_argument("--eth-reset-time",         default="10e-3",        help="Duration of Ethernet PHY reset.")
     parser.add_target_argument("--with-hyperram",          action="store_true",    help="Add HyperRAM.")
     parser.add_target_argument("--with-sdcard",            action="store_true",    help="Add SDCard.")
-    parser.add_target_argument("--with-jtagbone",          action="store_true",    help="Add JTAGBone.")
     parser.add_target_argument("--with-uartbone",          action="store_true",    help="Add UartBone on 2nd serial.")
     parser.add_target_argument("--with-video-terminal",    action="store_true",    help="Enable Video Terminal (HDMI).")
     parser.add_target_argument("--with-video-framebuffer", action="store_true",    help="Enable Video Framebuffer (HDMI).")
@@ -223,7 +221,6 @@ def main():
         eth_dynamic_ip         = args.eth_dynamic_ip,
         with_hyperram          = args.with_hyperram,
         with_sdcard            = args.with_sdcard,
-        with_jtagbone          = args.with_jtagbone,
         with_uartbone          = args.with_uartbone,
         with_spi_flash         = args.with_spi_flash,
         with_video_terminal    = args.with_video_terminal,
diff --git a/litex_boards/targets/antmicro_lpddr4_test_board.py b/litex_boards/targets/antmicro_lpddr4_test_board.py
index 55e0e58..c6adbc4 100755
--- a/litex_boards/targets/antmicro_lpddr4_test_board.py
+++ b/litex_boards/targets/antmicro_lpddr4_test_board.py
@@ -55,7 +55,6 @@ class BaseSoC(SoCCore):
             eth_dynamic_ip  = False,
             with_hyperram   = False,
             with_sdcard     = False,
-            with_jtagbone   = True,
             with_uartbone   = False,
             with_led_chaser = True,
             **kwargs):
@@ -104,10 +103,6 @@ class BaseSoC(SoCCore):
             if with_etherbone:
                 self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # UartBone ---------------------------------------------------------------------------------
         if with_uartbone:
             self.add_uartbone(baudrate=1e6)
@@ -133,7 +128,6 @@ def main():
     parser.add_target_argument("--eth-dynamic-ip",   action="store_true",    help="Enable dynamic Ethernet IP addresses setting.")
     parser.add_target_argument("--with-hyperram",    action="store_true",    help="Add HyperRAM.")
     parser.add_target_argument("--with-sdcard",      action="store_true",    help="Add SDCard.")
-    parser.add_target_argument("--with-jtagbone",    action="store_true",    help="Add JTAGBone.")
     parser.add_target_argument("--with-uartbone",    action="store_true",    help="Add UartBone on 2nd serial.")
     args = parser.parse_args()
 
@@ -148,7 +142,6 @@ def main():
         eth_dynamic_ip    = args.eth_dynamic_ip,
         with_hyperram     = args.with_hyperram,
         with_sdcard       = args.with_sdcard,
-        with_jtagbone     = args.with_jtagbone,
         with_uartbone     = args.with_uartbone,
         **parser.soc_argdict)
     builder = Builder(soc, **parser.builder_argdict)
diff --git a/litex_boards/targets/arduino_mkrvidor4000.py b/litex_boards/targets/arduino_mkrvidor4000.py
index bde45fe..85a11a6 100755
--- a/litex_boards/targets/arduino_mkrvidor4000.py
+++ b/litex_boards/targets/arduino_mkrvidor4000.py
@@ -55,9 +55,9 @@ class BaseSoC(SoCCore):
         self.crg = _CRG(platform, sys_clk_freq)
 
         # SoCCore ----------------------------------------------------------------------------------
-        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on MKR Vidor 4000", **kwargs)
+        kwargs["with_jtagbone"] = True # TODO: untested
 
-        self.add_jtagbone() # TODO: untested
+        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on MKR Vidor 4000", **kwargs)
 
         # SDR SDRAM --------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
diff --git a/litex_boards/targets/colorlight_i9plus.py b/litex_boards/targets/colorlight_i9plus.py
index fd19618..28df1bf 100755
--- a/litex_boards/targets/colorlight_i9plus.py
+++ b/litex_boards/targets/colorlight_i9plus.py
@@ -84,7 +84,6 @@ class BaseSoC(SoCCore):
         eth_ip          = "192.168.1.50",
         eth_dynamic_ip  = False,
         with_led_chaser = True,
-        with_jtagbone   = True,
         with_spi_flash  = False,
         **kwargs):
         platform = colorlight_i9plus.Platform(toolchain=toolchain)
@@ -127,10 +126,6 @@ class BaseSoC(SoCCore):
             if with_etherbone:
                 self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # SPI Flash --------------------------------------------------------------------------------
         if with_spi_flash:
             from litespi.modules import MX25L12833F
@@ -160,7 +155,6 @@ def main():
     parser.add_target_argument("--eth-port",       default=0, type=int,       help="Ethernet port to use (0/1)")
     parser.add_target_argument("--eth-ip",         default="192.168.1.50",    help="Ethernet/Etherbone IP address.")
     parser.add_target_argument("--eth-dynamic-ip", action="store_true",       help="Enable dynamic Ethernet IP addresses setting.")
-    parser.add_target_argument("--with-jtagbone",  action="store_true",       help="Enable JTAGbone support.")
     parser.add_target_argument("--with-spi-flash", action="store_true",       help="Enable SPI Flash (MMAPed).")
     args = parser.parse_args()
 
@@ -176,7 +170,6 @@ def main():
         eth_port       = args.eth_port,
         eth_ip         = args.eth_ip,
         eth_dynamic_ip = args.eth_dynamic_ip,
-        with_jtagbone  = args.with_jtagbone,
         with_spi_flash = args.with_spi_flash,
         **parser.soc_argdict
     )
diff --git a/litex_boards/targets/decklink_quad_hdmi_recorder.py b/litex_boards/targets/decklink_quad_hdmi_recorder.py
index 058f13f..9399762 100755
--- a/litex_boards/targets/decklink_quad_hdmi_recorder.py
+++ b/litex_boards/targets/decklink_quad_hdmi_recorder.py
@@ -69,12 +69,10 @@ class BaseSoC(SoCCore):
         self.crg = _CRG(platform, sys_clk_freq)
 
         # SoCCore ----------------------------------------------------------------------------------
-        kwargs["uart_name"] = "crossover"
+        kwargs["uart_name"]    = "crossover"
+        kwargs["with_jtabone"] = True
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Blackmagic Decklink Quad HDMI Recorder", **kwargs)
 
-        # JTAGBone  --------------------------------------------------------------------------------
-        self.add_jtagbone()
-
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.ddrphy = usddrphy.USDDRPHY(
diff --git a/litex_boards/targets/digilent_arty.py b/litex_boards/targets/digilent_arty.py
index 2c581f3..6b45675 100755
--- a/litex_boards/targets/digilent_arty.py
+++ b/litex_boards/targets/digilent_arty.py
@@ -78,7 +78,6 @@ class BaseSoC(SoCCore):
         eth_ip          = "192.168.1.50",
         eth_dynamic_ip  = False,
         with_led_chaser = True,
-        with_jtagbone   = True,
         with_spi_flash  = False,
         with_buttons    = False,
         with_pmod_gpio  = False,
@@ -123,10 +122,6 @@ class BaseSoC(SoCCore):
             if with_etherbone:
                 self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # SPI Flash --------------------------------------------------------------------------------
         if with_spi_flash:
             from litespi.modules import S25FL128L
@@ -174,7 +169,6 @@ def main():
     sdopts.add_argument("--with-spi-sdcard",       action="store_true", help="Enable SPI-mode SDCard support.")
     sdopts.add_argument("--with-sdcard",           action="store_true", help="Enable SDCard support.")
     parser.add_target_argument("--sdcard-adapter",                      help="SDCard PMOD adapter (digilent or numato).")
-    parser.add_target_argument("--with-jtagbone",  action="store_true", help="Enable JTAGbone support.")
     parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
     parser.add_target_argument("--with-pmod-gpio", action="store_true", help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
     args = parser.parse_args()
@@ -191,7 +185,6 @@ def main():
         with_etherbone = args.with_etherbone,
         eth_ip         = args.eth_ip,
         eth_dynamic_ip = args.eth_dynamic_ip,
-        with_jtagbone  = args.with_jtagbone,
         with_spi_flash = args.with_spi_flash,
         with_pmod_gpio = args.with_pmod_gpio,
         **parser.soc_argdict
diff --git a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py
index c4a9d74..4bf6447 100755
--- a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py
+++ b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py
@@ -53,7 +53,6 @@ class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=200e6,
         with_spi_flash = False,
         with_hyperram  = False,
-        with_jtagbone  = False,
         with_ethernet  = False,
         with_etherbone = False,
         eth_phy        = 0,
@@ -67,10 +66,6 @@ class BaseSoC(SoCCore):
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Efinix Titanium Ti60 F225 Dev Kit", **kwargs)
 
-        # JTAGBone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # SPI Flash --------------------------------------------------------------------------------
         if with_spi_flash:
             from litespi.modules import W25Q64JW
@@ -122,7 +117,6 @@ def main():
     parser.add_target_argument("--sys-clk-freq",   default=200e6, type=float, help="System clock frequency.")
     parser.add_target_argument("--with-spi-flash", action="store_true",       help="Enable SPI Flash (MMAPed).")
     parser.add_target_argument("--with-hyperram",  action="store_true",       help="Enable HyperRAM.")
-    parser.add_target_argument("--with-jtagbone",  action="store_true",       help="Enable JTAGbone support.")
     sdopts = parser.target_group.add_mutually_exclusive_group()
     sdopts.add_argument("--with-spi-sdcard",      action="store_true", help="Enable SPI-mode SDCard support.")
     sdopts.add_argument("--with-sdcard",          action="store_true", help="Enable SDCard support.")
@@ -137,7 +131,6 @@ def main():
         sys_clk_freq   = args.sys_clk_freq,
         with_spi_flash = args.with_spi_flash,
         with_hyperram  = args.with_hyperram,
-        with_jtagbone  = args.with_jtagbone,
         with_ethernet  = args.with_ethernet,
         with_etherbone = args.with_etherbone,
         eth_ip         = args.eth_ip,
diff --git a/litex_boards/targets/isx_im1283.py b/litex_boards/targets/isx_im1283.py
index bf4775e..1823517 100755
--- a/litex_boards/targets/isx_im1283.py
+++ b/litex_boards/targets/isx_im1283.py
@@ -51,7 +51,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=80e6, with_led_chaser=True, with_jtagbone=True, **kwargs):
+    def __init__(self, sys_clk_freq=80e6, with_led_chaser=True, **kwargs):
         platform = isx_im1283.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -62,10 +62,6 @@ class BaseSoC(SoCCore):
         # CRG --------------------------------------------------------------------------------------
         self.crg = _CRG(platform, sys_clk_freq)
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
@@ -90,7 +86,6 @@ def main():
     from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=isx_im1283.Platform, description="LiteX SoC on iM1283.")
     parser.add_argument("--sys-clk-freq", default=80e6, type=float, help="System clock frequency.")
-    parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
     sdopts = parser.add_mutually_exclusive_group()
     sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
     sdopts.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support.")
@@ -98,7 +93,6 @@ def main():
 
     soc = BaseSoC(
         sys_clk_freq = args.sys_clk_freq,
-        with_jtagbone = args.with_jtagbone,
         **parser.soc_argdict
     )
     if args.with_spi_sdcard:
diff --git a/litex_boards/targets/lattice_ecp5_evn.py b/litex_boards/targets/lattice_ecp5_evn.py
index 36ac571..304e137 100755
--- a/litex_boards/targets/lattice_ecp5_evn.py
+++ b/litex_boards/targets/lattice_ecp5_evn.py
@@ -46,7 +46,6 @@ class _CRG(LiteXModule):
 class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=50e6, toolchain="trellis", x5_clk_freq=None,
         with_led_chaser = True,
-        with_jtagbone   = True,
         **kwargs):
         platform = lattice_ecp5_evn.Platform(toolchain=toolchain)
 
@@ -56,10 +55,6 @@ class BaseSoC(SoCCore):
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ECP5 Evaluation Board", **kwargs)
 
-        # JtagBone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
             self.leds = LedChaser(
@@ -73,14 +68,12 @@ def main():
     parser = LiteXArgumentParser(platform=lattice_ecp5_evn.Platform, description="LiteX SoC on ECP5 Evaluation Board.")
     parser.add_target_argument("--sys-clk-freq", default=60e6, type=float, help="System clock frequency.")
     parser.add_target_argument("--x5-clk-freq",  type=int,                 help="Use X5 oscillator as system clock at the specified frequency.")
-    parser.add_target_argument("--with-jtagbone", action="store_true",     help="Add JTAGBone.")
     args = parser.parse_args()
 
     soc = BaseSoC(
         toolchain    = args.toolchain,
         sys_clk_freq = args.sys_clk_freq,
         x5_clk_freq  = args.x5_clk_freq,
-        with_jtagbone = args.with_jtagbone,
         **parser.soc_argdict)
     builder = Builder(soc, **parser.builder_argdict)
     if args.build:
diff --git a/litex_boards/targets/limesdr_mini_v2.py b/litex_boards/targets/limesdr_mini_v2.py
index 1e35774..e123dca 100755
--- a/litex_boards/targets/limesdr_mini_v2.py
+++ b/litex_boards/targets/limesdr_mini_v2.py
@@ -75,12 +75,10 @@ class BaseSoC(SoCCore):
         platform = limesdr_mini_v2.Platform(toolchain=toolchain)
 
         # SoCCore ----------------------------------------------------------------------------------
-        kwargs["uart_name"] = "crossover"
+        kwargs["uart_name"]     = "crossover"
+        kwargs["with_jtagbone"] = True
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on LimeSDR-Mini-V2", **kwargs)
 
-        # JTAGBone ---------------------------------------------------------------------------------
-        self.add_jtagbone()
-
         # CRG --------------------------------------------------------------------------------------
         self.crg = _CRG(platform, sys_clk_freq)
 
diff --git a/litex_boards/targets/mnt_rkx7.py b/litex_boards/targets/mnt_rkx7.py
index 938f10c..d0de20e 100755
--- a/litex_boards/targets/mnt_rkx7.py
+++ b/litex_boards/targets/mnt_rkx7.py
@@ -94,6 +94,7 @@ class BaseSoC(SoCCore):
         self.crg = _CRG(platform, sys_clk_freq)
 
         # SoCCore ----------------------------------------------------------------------------------
+        #kwargs["with_jtagbone"] = True
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on MNT-RKX7", **kwargs)
 
         # DDR3 SDRAM -------------------------------------------------------------------------------
@@ -142,9 +143,6 @@ class BaseSoC(SoCCore):
         self.i2c1 = I2CMaster(platform.request("i2c", 1))
         self.i2c2 = I2CMaster(platform.request("i2c", 2))
 
-        # JTAG -------------------------------------------------------------------------------------
-        #self.add_jtagbone()
-
         # Backlight --------------------------------------------------------------------------------
         # Motherboard display connector backlight, currently unused (the new backlight signals
         # are on the 50pin RGB->eDP connector)
diff --git a/litex_boards/targets/newae_cw305.py b/litex_boards/targets/newae_cw305.py
index 78d403e..80434e4 100755
--- a/litex_boards/targets/newae_cw305.py
+++ b/litex_boards/targets/newae_cw305.py
@@ -65,12 +65,10 @@ class BaseSoC(SoCCore):
         self.crg = _CRG(platform, sys_clk_freq)
 
         # SoCCore ----------------------------------------------------------------------------------
-        kwargs["uart_name"] = "crossover"
+        kwargs["uart_name"]     = "crossover"
+        kwargs["with_jtagbone"] = True
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on NewAE-CW305", **kwargs)
 
-        # JTAGBone ---------------------------------------------------------------------------------
-        self.add_jtagbone()
-
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
             self.leds = LedChaser(
diff --git a/litex_boards/targets/qmtech_artix7_fbg484.py b/litex_boards/targets/qmtech_artix7_fbg484.py
index 294e801..3df096a 100755
--- a/litex_boards/targets/qmtech_artix7_fbg484.py
+++ b/litex_boards/targets/qmtech_artix7_fbg484.py
@@ -75,7 +75,6 @@ class BaseSoC(SoCCore):
         with_led_chaser        = True,
         with_video_terminal    = False,
         with_video_framebuffer = False,
-        with_jtagbone          = True,
         with_spi_flash         = False,
         **kwargs):
         platform = qmtech_artix7_fbg484.Platform(kgates=kgates, toolchain=toolchain, with_daughterboard=with_daughterboard)
@@ -117,10 +116,6 @@ class BaseSoC(SoCCore):
             # The daughterboard has the tx clock wired to a non-clock pin, so we can't help it
             self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]")
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # SPI Flash --------------------------------------------------------------------------------
         if with_spi_flash:
             from litespi.modules import MT25QL128
@@ -160,7 +155,6 @@ def main():
     sdopts = parser.target_group.add_mutually_exclusive_group()
     sdopts.add_argument("--with-spi-sdcard",       action="store_true", help="Enable SPI-mode SDCard support.")
     sdopts.add_argument("--with-sdcard",           action="store_true", help="Enable SDCard support.")
-    parser.add_target_argument("--with-jtagbone",  action="store_true", help="Enable Jtagbone support.")
     parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
     viopts = parser.target_group.add_mutually_exclusive_group()
     viopts.add_argument("--with-video-terminal",    action="store_true", help="Enable Video Terminal (VGA).")
@@ -176,7 +170,6 @@ def main():
         with_etherbone         = args.with_etherbone,
         eth_ip                 = args.eth_ip,
         eth_dynamic_ip         = args.eth_dynamic_ip,
-        with_jtagbone          = args.with_jtagbone,
         with_spi_flash         = args.with_spi_flash,
         with_video_terminal    = args.with_video_terminal,
         with_video_framebuffer = args.with_video_framebuffer,
diff --git a/litex_boards/targets/qmtech_artix7_fgg676.py b/litex_boards/targets/qmtech_artix7_fgg676.py
index 5d71ced..9793a3c 100755
--- a/litex_boards/targets/qmtech_artix7_fgg676.py
+++ b/litex_boards/targets/qmtech_artix7_fgg676.py
@@ -75,7 +75,6 @@ class BaseSoC(SoCCore):
         with_led_chaser        = True,
         with_video_terminal    = False,
         with_video_framebuffer = False,
-        with_jtagbone          = True,
         with_spi_flash         = False,
         **kwargs):
         platform = qmtech_artix7_fgg676.Platform(kgates=kgates, toolchain=toolchain, with_daughterboard=with_daughterboard)
@@ -117,10 +116,6 @@ class BaseSoC(SoCCore):
             # The daughterboard has the tx clock wired to a non-clock pin, so we can't help it
             self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]")
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # SPI Flash --------------------------------------------------------------------------------
         if with_spi_flash:
             from litespi.modules import MT25QL128
@@ -160,7 +155,6 @@ def main():
     sdopts = parser.target_group.add_mutually_exclusive_group()
     sdopts.add_argument("--with-spi-sdcard",       action="store_true", help="Enable SPI-mode SDCard support.")
     sdopts.add_argument("--with-sdcard",           action="store_true", help="Enable SDCard support.")
-    parser.add_target_argument("--with-jtagbone",  action="store_true", help="Enable Jtagbone support.")
     parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
     viopts = parser.target_group.add_mutually_exclusive_group()
     viopts.add_argument("--with-video-terminal",    action="store_true", help="Enable Video Terminal (VGA).")
@@ -176,7 +170,6 @@ def main():
         with_etherbone         = args.with_etherbone,
         eth_ip                 = args.eth_ip,
         eth_dynamic_ip         = args.eth_dynamic_ip,
-        with_jtagbone          = args.with_jtagbone,
         with_spi_flash         = args.with_spi_flash,
         with_video_terminal    = args.with_video_terminal,
         with_video_framebuffer = args.with_video_framebuffer,
diff --git a/litex_boards/targets/qmtech_ep4ce15_starter_kit.py b/litex_boards/targets/qmtech_ep4ce15_starter_kit.py
index 5f36fcf..7726fc5 100755
--- a/litex_boards/targets/qmtech_ep4ce15_starter_kit.py
+++ b/litex_boards/targets/qmtech_ep4ce15_starter_kit.py
@@ -61,8 +61,6 @@ class _CRG(LiteXModule):
 
 class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=50e6,
-        with_jtaguart   = False,
-        with_jtagbone   = False,
         with_led_chaser = True,
         sdram_rate      = "1:1",
         **kwargs):
@@ -72,20 +70,14 @@ class BaseSoC(SoCCore):
         self.crg = _CRG(platform, sys_clk_freq, sdram_rate = sdram_rate)
 
         # SoCCore ----------------------------------------------------------------------------------
-        if with_jtagbone:
+        if kwargs["with_jtagbone"]:
             kwargs["uart_name"] = "crossover"
-        if with_jtaguart:
-            kwargs["uart_name"] = "jtag_uart"
 
         SoCCore.__init__(self, platform, sys_clk_freq,
             ident = "LiteX SoC on QMTECH Cyclone IV Starter Kit",
             **kwargs
         )
 
-        # JTAGbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # SDR SDRAM --------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
@@ -111,15 +103,11 @@ def main():
     parser = LiteXArgumentParser(platform=qmtech_ep4ce15_starter_kit.Platform, description="LiteX SoC on QMTECH EP4CE15")
     parser.add_target_argument("--sys-clk-freq",  default=50e6, type=float, help="System clock frequency.")
     parser.add_target_argument("--sdram-rate",    default="1:1",            help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
-    parser.add_target_argument("--with-jtaguart", action="store_true",      help="Enable JTAGUart support.")
-    parser.add_target_argument("--with-jtagbone", action="store_true",      help="Enable JTAGbone support.")
     args = parser.parse_args()
 
     soc = BaseSoC(
         sys_clk_freq           = args.sys_clk_freq,
         sdram_rate             = args.sdram_rate,
-        with_jtagbone          = args.with_jtagbone,
-        with_jtaguart          = args.with_jtaguart,
         **parser.soc_argdict
     )
 
diff --git a/litex_boards/targets/qmtech_xc7a35t.py b/litex_boards/targets/qmtech_xc7a35t.py
index 5d41d36..b8205d6 100755
--- a/litex_boards/targets/qmtech_xc7a35t.py
+++ b/litex_boards/targets/qmtech_xc7a35t.py
@@ -75,7 +75,6 @@ class BaseSoC(SoCCore):
         with_led_chaser        = True,
         with_video_terminal    = False,
         with_video_framebuffer = False,
-        with_jtagbone          = True,
         with_spi_flash         = False,
         **kwargs):
         platform = qmtech_xc7a35t.Platform(toolchain=toolchain, with_daughterboard=with_daughterboard)
@@ -117,10 +116,6 @@ class BaseSoC(SoCCore):
             # The daughterboard has the tx clock wired to a non-clock pin, so we can't help it
             self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]")
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # SPI Flash --------------------------------------------------------------------------------
         if with_spi_flash:
             from litespi.modules import MT25QL128
@@ -159,7 +154,6 @@ def main():
     sdopts = parser.target_group.add_mutually_exclusive_group()
     sdopts.add_argument("--with-spi-sdcard",       action="store_true", help="Enable SPI-mode SDCard support.")
     sdopts.add_argument("--with-sdcard",           action="store_true", help="Enable SDCard support.")
-    parser.add_target_argument("--with-jtagbone",  action="store_true", help="Enable Jtagbone support.")
     parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
     viopts = parser.target_group.add_mutually_exclusive_group()
     viopts.add_argument("--with-video-terminal",    action="store_true", help="Enable Video Terminal (VGA).")
@@ -174,7 +168,6 @@ def main():
         with_etherbone         = args.with_etherbone,
         eth_ip                 = args.eth_ip,
         eth_dynamic_ip         = args.eth_dynamic_ip,
-        with_jtagbone          = args.with_jtagbone,
         with_spi_flash         = args.with_spi_flash,
         with_video_terminal    = args.with_video_terminal,
         with_video_framebuffer = args.with_video_framebuffer,
diff --git a/litex_boards/targets/qmtech_xc7k325t.py b/litex_boards/targets/qmtech_xc7k325t.py
index 1ba43b8..7cd1683 100755
--- a/litex_boards/targets/qmtech_xc7k325t.py
+++ b/litex_boards/targets/qmtech_xc7k325t.py
@@ -69,7 +69,7 @@ class BaseSoC(SoCCore):
                  with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
                  local_ip="", remote_ip="",
                  with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, with_video_colorbars=False,
-                 with_jtagbone=True, with_spi_flash=False, **kwargs):
+                 with_spi_flash=False, **kwargs):
         platform = qmtech_xc7k325t.Platform(toolchain=toolchain, with_daughterboard=with_daughterboard)
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -125,10 +125,6 @@ class BaseSoC(SoCCore):
             self.add_constant("REMOTEIP3", int(remote_ip[2]))
             self.add_constant("REMOTEIP4", int(remote_ip[3]))
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # SPI Flash --------------------------------------------------------------------------------
         if with_spi_flash:
             from litespi.modules import MT25QL128
@@ -182,7 +178,6 @@ def main():
     sdopts = parser.add_mutually_exclusive_group()
     sdopts.add_argument("--with-spi-sdcard",     action="store_true",              help="Enable SPI-mode SDCard support.")
     sdopts.add_argument("--with-sdcard",         action="store_true",              help="Enable SDCard support.")
-    parser.add_argument("--with-jtagbone",       action="store_true",              help="Enable Jtagbone support.")
     parser.add_argument("--with-spi-flash",      action="store_true",              help="Enable SPI Flash (MMAPed).")
     viopts = parser.add_mutually_exclusive_group()
     viopts.add_argument("--with-video-terminal",    action="store_true", help="Enable Video Terminal (VGA).")
@@ -203,7 +198,6 @@ def main():
         eth_dynamic_ip         = args.eth_dynamic_ip,
         local_ip               = args.local_ip,
         remote_ip              = args.remote_ip,
-        with_jtagbone          = args.with_jtagbone,
         with_spi_flash         = args.with_spi_flash,
         with_video_terminal    = args.with_video_terminal,
         with_video_framebuffer = args.with_video_framebuffer,
diff --git a/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py b/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py
index 18bccfb..1d34412 100755
--- a/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py
+++ b/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py
@@ -64,7 +64,6 @@ class BaseSoC(SoCCore):
     
     def __init__(self, sys_clk_freq=100e6,
         with_led_chaser     = True,
-        with_jtagbone       = False,
         with_video_terminal = True,
         with_neopixel       = False,
         **kwargs):
@@ -77,10 +76,6 @@ class BaseSoC(SoCCore):
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Seeedstudio Spartan Edge Accelerator", **kwargs)
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
             self.leds = LedChaser(
@@ -108,14 +103,12 @@ def main():
     from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=seeedstudio_spartan_edge_accelerator.Platform, description="LiteX SoC on Spartan Edge Accelerator.")
     parser.add_target_argument("--sys-clk-freq",        default=100e6, type=float, help="System clock frequency.")
-    parser.add_target_argument("--with-jtagbone",       action="store_true",       help="Enable Jtagbone support.")
     parser.add_target_argument("--with-video-terminal", action="store_true",       help="Enable Video Colorbars (HDMI).")
     parser.add_target_argument("--with-neopixel",       action="store_true",       help="Enable onboard 2 Neopixels Leds.")
 
     args = parser.parse_args()
     soc = BaseSoC(
         sys_clk_freq        = args.sys_clk_freq,
-        with_jtagbone       = args.with_jtagbone,
         with_video_terminal = args.with_video_terminal,
         with_neopixel       = args.with_neopixel,
         **parser.soc_argdict
diff --git a/litex_boards/targets/sitlinv_stlv7325_v1.py b/litex_boards/targets/sitlinv_stlv7325_v1.py
index dd2bc6b..8f30fc3 100755
--- a/litex_boards/targets/sitlinv_stlv7325_v1.py
+++ b/litex_boards/targets/sitlinv_stlv7325_v1.py
@@ -80,7 +80,6 @@ class BaseSoC(SoCCore):
         with_led_chaser        = True,
         with_pcie              = False,
         with_sata              = False,
-        with_jtagbone          = True,
         with_video_colorbars   = False,
         with_video_framebuffer = False,
         with_video_terminal    = False,
@@ -106,10 +105,6 @@ class BaseSoC(SoCCore):
                 l2_cache_size = kwargs.get("l2_size", 8192),
             )
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # Ethernet / Etherbone ---------------------------------------------------------------------
         if with_ethernet or with_etherbone:
             self.ethphy = LiteEthPHY(
@@ -200,7 +195,6 @@ def main():
     parser.add_target_argument("--with-pcie",       action="store_true",    help="Enable PCIe support.")
     parser.add_target_argument("--driver",          action="store_true",    help="Generate PCIe driver.")
     parser.add_target_argument("--with-sata",       action="store_true",    help="Enable SATA support.")
-    parser.add_target_argument("--with-jtagbone",   action="store_true",    help="Enable Jtagbone support.")
     sdopts = parser.target_group.add_mutually_exclusive_group()
     sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
     sdopts.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support.")
@@ -222,7 +216,6 @@ def main():
         eth_dynamic_ip         = args.eth_dynamic_ip,
         with_pcie              = args.with_pcie,
         with_sata              = args.with_sata,
-        with_jtagbone          = args.with_jtagbone,
         with_video_colorbars   = args.with_video_colorbars,
         with_video_framebuffer = args.with_video_framebuffer,
         with_video_terminal    = args.with_video_terminal,
diff --git a/litex_boards/targets/sitlinv_stlv7325_v2.py b/litex_boards/targets/sitlinv_stlv7325_v2.py
index afcd61c..ccda71a 100755
--- a/litex_boards/targets/sitlinv_stlv7325_v2.py
+++ b/litex_boards/targets/sitlinv_stlv7325_v2.py
@@ -77,7 +77,6 @@ class BaseSoC(SoCCore):
         with_led_chaser        = True,
         with_pcie              = False,
         with_sata              = False, sata_gen="gen2",
-        with_jtagbone          = False,
         with_video_colorbars   = False,
         with_video_framebuffer = False,
         with_video_terminal    = False,
@@ -103,10 +102,6 @@ class BaseSoC(SoCCore):
                 l2_cache_size = kwargs.get("l2_size", 8192),
             )
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # Ethernet / Etherbone ---------------------------------------------------------------------
         if with_ethernet:
             self.ethphy = LiteEthPHYRGMII(
@@ -178,7 +173,6 @@ def main():
     parser.add_target_argument("--with-ethernet",   action="store_true",    help="Enable Ethernet support.")
     parser.add_target_argument("--with-sata",       action="store_true",    help="Enable SATA support.")
     parser.add_target_argument("--sata-gen",        default="2",    help="SATA Gen..", choices=["1", "2", "3"])
-    parser.add_target_argument("--with-jtagbone",   action="store_true",    help="Enable Jtagbone support.")
     sdopts = parser.target_group.add_mutually_exclusive_group()
     sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
     sdopts.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support.")
@@ -195,7 +189,6 @@ def main():
         with_pcie              = args.with_pcie,
         with_sata              = args.with_sata,
         sata_gen               = "gen" + args.sata_gen,
-        with_jtagbone          = args.with_jtagbone,
         with_video_colorbars   = args.with_video_colorbars,
         with_video_framebuffer = args.with_video_framebuffer,
         with_video_terminal    = args.with_video_terminal,
diff --git a/litex_boards/targets/sqrl_fk33.py b/litex_boards/targets/sqrl_fk33.py
index 9fac732..04fc536 100755
--- a/litex_boards/targets/sqrl_fk33.py
+++ b/litex_boards/targets/sqrl_fk33.py
@@ -73,11 +73,10 @@ class BaseSoC(SoCCore):
         # SoCCore ----------------------------------------------------------------------------------
         if kwargs.get("uart_name", "serial") == "serial":
             kwargs["uart_name"] = "crossover" # Defaults to Crossover-UART.
+        kwargs["with_jtagbone"]  = True
+        kwargs["jtagbone_chain"] = 2 # Chain 1 already used by HBM2 debug probes.
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on FK33", **kwargs)
 
-        # JTAGBone --------------------------------------------------------------------------------
-        self.add_jtagbone(chain=2) # Chain 1 already used by HBM2 debug probes.
-
         # HBM --------------------------------------------------------------------------------------
         if with_hbm:
             # Add HBM Core.
diff --git a/litex_boards/targets/terasic_deca.py b/litex_boards/targets/terasic_deca.py
index 45d9ab5..1ad5e45 100755
--- a/litex_boards/targets/terasic_deca.py
+++ b/litex_boards/targets/terasic_deca.py
@@ -59,7 +59,6 @@ class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=50e6,
         with_led_chaser     = True,
         with_uartbone       = False,
-        with_jtagbone       = False,
         with_video_terminal = False,
         with_spi_sdcard     = False,
         with_ethernet       = False,
@@ -76,7 +75,7 @@ class BaseSoC(SoCCore):
         # Defaults to JTAG-UART since no hardware UART.
         real_uart_name = kwargs["uart_name"]
         if real_uart_name == "serial":
-            if with_jtagbone:
+            if kwargs["with_jtagbone"]:
                 kwargs["uart_name"] = "crossover"
             else:
                 kwargs["uart_name"] = "jtag_uart"
@@ -88,10 +87,6 @@ class BaseSoC(SoCCore):
         if with_uartbone:
             self.add_uartbone(uart_name=real_uart_name, baudrate=kwargs["uart_baudrate"])
 
-        # JTAGbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # Ethernet ---------------------------------------------------------------------------------
         if with_ethernet or with_etherbone:
             self.platform.toolchain.additional_sdc_commands += [
@@ -150,7 +145,6 @@ def main():
     parser.add_target_argument("--eth-ip",              default="192.168.1.50", help="Ethernet/Etherbone IP address.")
     parser.add_target_argument("--eth-dynamic-ip",      action="store_true",    help="Enable dynamic Ethernet IP addresses setting.")
     parser.add_target_argument("--with-uartbone",       action="store_true",    help="Enable UARTbone support.")
-    parser.add_target_argument("--with-jtagbone",       action="store_true",    help="Enable JTAGbone support.")
     parser.add_target_argument("--with-video-terminal", action="store_true",    help="Enable Video Terminal (VGA).")
     parser.add_target_argument("--with-spi-sdcard",     action="store_true",    help="Enable SPI SD card controller.")
     args = parser.parse_args()
@@ -162,7 +156,6 @@ def main():
         eth_ip              = args.eth_ip,
         eth_dynamic_ip      = args.eth_dynamic_ip,
         with_uartbone       = args.with_uartbone,
-        with_jtagbone       = args.with_jtagbone,
         with_video_terminal = args.with_video_terminal,
         with_spi_sdcard     = args.with_spi_sdcard,
         **parser.soc_argdict
diff --git a/litex_boards/targets/xilinx_alveo_u280.py b/litex_boards/targets/xilinx_alveo_u280.py
index d57aa7a..3d4f8cf 100755
--- a/litex_boards/targets/xilinx_alveo_u280.py
+++ b/litex_boards/targets/xilinx_alveo_u280.py
@@ -102,13 +102,12 @@ class BaseSoC(SoCCore):
         self.crg = _CRG(platform, sys_clk_freq, ddram_channel, with_hbm)
 
         # SoCCore ----------------------------------------------------------------------------------
+        kwargs["jtagbone_chain"] = 2 # Chain 1 already used by HBM2 debug probes.
+
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alveo U280 (ES1)", **kwargs)
 
         # HBM / DRAM -------------------------------------------------------------------------------
         if with_hbm:
-            # JTAGBone -----------------------------------------------------------------------------
-            #self.add_jtagbone(chain=2) # Chain 1 already used by HBM2 debug probes.
-
             # Add HBM Core.
             self.hbm = hbm = ClockDomainsRenamer({"axi": "sys"})(USPHBM2(platform))