From a72f2a2e6859d472784c9c9866137e9a954d7fe1 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Fri, 29 Mar 2024 07:18:19 +0100 Subject: [PATCH] targets/xilinx_zc706: typo... --- litex_boards/targets/xilinx_zc706.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/xilinx_zc706.py b/litex_boards/targets/xilinx_zc706.py index c46db4b..08bbaa8 100755 --- a/litex_boards/targets/xilinx_zc706.py +++ b/litex_boards/targets/xilinx_zc706.py @@ -93,7 +93,7 @@ class BaseSoC(SoCCore): # When nor jtagbone, nor etherbone are set forces jtagbone. kwargs["uart_name"] = "crossover" - if kwargs["with_jtagbone"] or with_etherbone: + if not (kwargs["with_jtagbone"] or with_etherbone): kwargs["with_jtagbone"] = True # CRG --------------------------------------------------------------------------------------