diff --git a/litex_boards/partner/targets/netv2.py b/litex_boards/partner/targets/netv2.py
index 6885916..554b410 100755
--- a/litex_boards/partner/targets/netv2.py
+++ b/litex_boards/partner/targets/netv2.py
@@ -27,6 +27,7 @@ class _CRG(Module):
         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()
+        self.clock_domains.cd_clk100 = ClockDomain()
         self.clock_domains.cd_eth = ClockDomain()
 
         # # #
@@ -41,6 +42,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_clk200, 200e6)
+        pll.create_clkout(self.cd_clk100, 100e6)
         pll.create_clkout(self.cd_eth, 50e6)
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)