diff --git a/litex_boards/platforms/terasic_de10nano.py b/litex_boards/platforms/terasic_de10nano.py
index be436a0..5743afa 100644
--- a/litex_boards/platforms/terasic_de10nano.py
+++ b/litex_boards/platforms/terasic_de10nano.py
@@ -67,7 +67,7 @@ _io = [
 
     # HDMI
     ("hdmi", 0,
-        Subsignal("tx_d_r", Pins("AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5")),
+        Subsignal("tx_d_r", Pins("AD12 AE12 W8 Y8 AD11 AD10 AE11 Y5")),
         Subsignal("tx_d_g", Pins("AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5")),
         Subsignal("tx_d_b", Pins("AE4 AH2 AH4 AH5 AH6 AG6 AF9 AE8")),
         Subsignal("tx_clk", Pins("AG5")),
diff --git a/litex_boards/targets/xilinx_alveo_u200.py b/litex_boards/targets/xilinx_alveo_u200.py
index b817ce9..ce91458 100755
--- a/litex_boards/targets/xilinx_alveo_u200.py
+++ b/litex_boards/targets/xilinx_alveo_u200.py
@@ -75,6 +75,7 @@ class BaseSoC(SoCCore):
             self.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
                 memtype          = "DDR4",
                 sys_clk_freq     = sys_clk_freq,
+                cmd_latency      = 1,
                 iodelay_clk_freq = 500e6,
                 is_rdimm         = True)
             self.add_sdram("sdram",
diff --git a/litex_boards/targets/xilinx_alveo_u250.py b/litex_boards/targets/xilinx_alveo_u250.py
index 247e32b..b5d457d 100755
--- a/litex_boards/targets/xilinx_alveo_u250.py
+++ b/litex_boards/targets/xilinx_alveo_u250.py
@@ -74,6 +74,7 @@ class BaseSoC(SoCCore):
             self.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
                 memtype          = "DDR4",
                 sys_clk_freq     = sys_clk_freq,
+                cmd_latency      = 1,
                 iodelay_clk_freq = 500e6,
                 is_rdimm         = True)
             self.add_sdram("sdram",