From 340da5393c54a3fe0d186d2ad940114b8f29f21b Mon Sep 17 00:00:00 2001 From: Do Viet Thanh Date: Mon, 17 Apr 2023 18:59:50 +0700 Subject: [PATCH 1/3] Fix Memory initialization of Alveo U200 failed #1606 --- litex_boards/targets/xilinx_alveo_u200.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex_boards/targets/xilinx_alveo_u200.py b/litex_boards/targets/xilinx_alveo_u200.py index b817ce9..ce91458 100755 --- a/litex_boards/targets/xilinx_alveo_u200.py +++ b/litex_boards/targets/xilinx_alveo_u200.py @@ -75,6 +75,7 @@ class BaseSoC(SoCCore): self.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), memtype = "DDR4", sys_clk_freq = sys_clk_freq, + cmd_latency = 1, iodelay_clk_freq = 500e6, is_rdimm = True) self.add_sdram("sdram", From 03913e2e153825a3075fd80b86bd219791d1de53 Mon Sep 17 00:00:00 2001 From: 594rk <9329132+594rk@users.noreply.github.com> Date: Sun, 23 Apr 2023 22:28:00 -0500 Subject: [PATCH 2/3] Update terasic_de10nano.py Corrected pin number --- litex_boards/platforms/terasic_de10nano.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/platforms/terasic_de10nano.py b/litex_boards/platforms/terasic_de10nano.py index be436a0..5743afa 100644 --- a/litex_boards/platforms/terasic_de10nano.py +++ b/litex_boards/platforms/terasic_de10nano.py @@ -67,7 +67,7 @@ _io = [ # HDMI ("hdmi", 0, - Subsignal("tx_d_r", Pins("AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5")), + Subsignal("tx_d_r", Pins("AD12 AE12 W8 Y8 AD11 AD10 AE11 Y5")), Subsignal("tx_d_g", Pins("AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5")), Subsignal("tx_d_b", Pins("AE4 AH2 AH4 AH5 AH6 AG6 AF9 AE8")), Subsignal("tx_clk", Pins("AG5")), From 68bfb325a59fbbc40a707403d1df8bc2829221bc Mon Sep 17 00:00:00 2001 From: offNaria Date: Mon, 24 Apr 2023 17:35:58 +0900 Subject: [PATCH 3/3] Fix Memory test failure of Alveo U250 --- litex_boards/targets/xilinx_alveo_u250.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex_boards/targets/xilinx_alveo_u250.py b/litex_boards/targets/xilinx_alveo_u250.py index 247e32b..b5d457d 100755 --- a/litex_boards/targets/xilinx_alveo_u250.py +++ b/litex_boards/targets/xilinx_alveo_u250.py @@ -74,6 +74,7 @@ class BaseSoC(SoCCore): self.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), memtype = "DDR4", sys_clk_freq = sys_clk_freq, + cmd_latency = 1, iodelay_clk_freq = 500e6, is_rdimm = True) self.add_sdram("sdram",