From aaf8d54c6aa961002573215a72baba0b3d2558e2 Mon Sep 17 00:00:00 2001
From: Marcin Sloniewski <marcin.sloniewski@gmail.com>
Date: Wed, 8 Jan 2020 20:56:12 +0100
Subject: [PATCH] targets/de10lite: use AsyncResetSynchronizer for clock
 domains

At the start output of the pll is not stabilized, which
caused malfunctions when used for sys clock domain.
Use AsyncResetSynchronizer to start clock domains
on pll locked signal.
---
 litex_boards/community/targets/de10lite.py | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

diff --git a/litex_boards/community/targets/de10lite.py b/litex_boards/community/targets/de10lite.py
index 9bc9414..d4e7fd1 100755
--- a/litex_boards/community/targets/de10lite.py
+++ b/litex_boards/community/targets/de10lite.py
@@ -6,6 +6,7 @@
 import argparse
 
 from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex_boards.platforms import de10lite
 
@@ -24,7 +25,6 @@ class _CRG(Module):
     def __init__(self, platform):
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain()
-        self.clock_domains.cd_por    = ClockDomain(reset_less=True)
         self.clock_domains.cd_vga    = ClockDomain(reset_less=True)
 
         # # #
@@ -32,16 +32,8 @@ class _CRG(Module):
         # main input clock for PLL
         clk50 = platform.request("clk50")
 
-        # power on rst
-        rst_n = Signal()
-        self.sync.por += rst_n.eq(1)
-        self.comb += [
-            self.cd_por.clk.eq(clk50),
-            self.cd_sys.rst.eq(~rst_n),
-            self.cd_sys_ps.rst.eq(~rst_n)
-        ]
-
         # sys clk / sdram clk  / vga_clk from PLL
+        pll_locked  = Signal()
         pll_clk_out = Signal(6)
         self.specials += \
             Instance("ALTPLL",
@@ -65,18 +57,23 @@ class _CRG(Module):
                 p_OPERATION_MODE         = "NORMAL",
                 i_INCLK                  = clk50,
                 o_CLK                    = pll_clk_out,
-                i_ARESET                 = ~rst_n,
                 i_CLKENA                 = 0x3f,
                 i_EXTCLKENA              = 0xf,
                 i_FBIN                   = 1,
                 i_PFDENA                 = 1,
                 i_PLLENA                 = 1,
+                o_LOCKED                 = pll_locked,
             )
         self.comb += [
             self.cd_sys.clk.eq(pll_clk_out[0]),
             self.cd_sys_ps.clk.eq(pll_clk_out[1]),
             self.cd_vga.clk.eq(pll_clk_out[2])
         ]
+        self.specials += [
+            AsyncResetSynchronizer(self.cd_sys,    ~pll_locked),
+            AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked),
+            AsyncResetSynchronizer(self.cd_vga,    ~pll_locked),
+        ]
         self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
 
 # BaseSoC ------------------------------------------------------------------------------------------