From ab732011b32ff8ecf563cf769359158007a1280e Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 22 Jul 2024 14:49:03 +0200 Subject: [PATCH] plaforms/lattice_certuspro_nx_xx: SPI_MASTER_PORT disabled (required to have access to the flash), added default clk period constraints --- litex_boards/platforms/lattice_certuspro_nx_evn.py | 7 ++++++- litex_boards/platforms/lattice_certuspro_nx_versa.py | 7 ++++++- litex_boards/platforms/lattice_certuspro_nx_vvml.py | 7 ++++++- 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/litex_boards/platforms/lattice_certuspro_nx_evn.py b/litex_boards/platforms/lattice_certuspro_nx_evn.py index 57a0259..e3390be 100644 --- a/litex_boards/platforms/lattice_certuspro_nx_evn.py +++ b/litex_boards/platforms/lattice_certuspro_nx_evn.py @@ -137,9 +137,14 @@ class Platform(LatticeNexusPlatform): def __init__(self, device="LFCPNX", toolchain="radiant", **kwargs): assert device in ["LFCPNX"] LatticeNexusPlatform.__init__(self, device + "-100-9LFG672C", _io, _connectors, toolchain=toolchain, **kwargs) - self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}") + # SPI Pins may be used as General IO Pins (see FPGA-AN-02048 4.1.7) + self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=DISABLE}}") # Evaluation mode (with free license) self.toolchain.set_prj_strategy_opts({"bit_ip_eval": "true"}) def create_programmer(self): return OpenFPGALoader() + + def do_finalize(self, fragment): + LatticeNexusPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6) diff --git a/litex_boards/platforms/lattice_certuspro_nx_versa.py b/litex_boards/platforms/lattice_certuspro_nx_versa.py index 03c7fc5..f01bd18 100644 --- a/litex_boards/platforms/lattice_certuspro_nx_versa.py +++ b/litex_boards/platforms/lattice_certuspro_nx_versa.py @@ -136,9 +136,14 @@ class Platform(LatticeNexusPlatform): def __init__(self, device="LFCPNX", toolchain="radiant", **kwargs): assert device in ["LFCPNX"] LatticeNexusPlatform.__init__(self, device + "-100-9LFG672I", _io, _connectors, toolchain=toolchain, **kwargs) - self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}") + # SPI Pins may be used as General IO Pins (see FPGA-AN-02048 4.1.7) + self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=DISABLE}}") # Evaluation mode (with free license) self.toolchain.set_prj_strategy_opts({"bit_ip_eval": "true"}) def create_programmer(self): return OpenFPGALoader() + + def do_finalize(self, fragment): + LatticeNexusPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clkin125", loose=True), 1e9/125e6) diff --git a/litex_boards/platforms/lattice_certuspro_nx_vvml.py b/litex_boards/platforms/lattice_certuspro_nx_vvml.py index cce361d..4b7b9a3 100644 --- a/litex_boards/platforms/lattice_certuspro_nx_vvml.py +++ b/litex_boards/platforms/lattice_certuspro_nx_vvml.py @@ -110,9 +110,14 @@ class Platform(LatticeNexusPlatform): def __init__(self, device="LFCPNX", toolchain="radiant", **kwargs): assert device in ["LFCPNX"] LatticeNexusPlatform.__init__(self, device + "-100-9BBG484I", _io, _connectors, toolchain=toolchain, **kwargs) - self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}") + # SPI Pins may be used as General IO Pins (see FPGA-AN-02048 4.1.7) + self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=DISABLE}}") # Evaluation mode (with free license) self.toolchain.set_prj_strategy_opts({"bit_ip_eval": "true"}) def create_programmer(self): return OpenFPGALoader() + + def do_finalize(self, fragment): + LatticeNexusPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk24", loose=True), 1e9/24e6)