diff --git a/litex_boards/community/targets/ac701.py b/litex_boards/community/targets/ac701.py index 20d5811..e992967 100755 --- a/litex_boards/community/targets/ac701.py +++ b/litex_boards/community/targets/ac701.py @@ -8,7 +8,7 @@ import argparse from migen import * -from litex_boards.community.platforms import ac701 +from litex_boards.platforms import ac701 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import mem_decoder diff --git a/litex_boards/community/targets/de10lite.py b/litex_boards/community/targets/de10lite.py index 31e9371..eb7a5f1 100755 --- a/litex_boards/community/targets/de10lite.py +++ b/litex_boards/community/targets/de10lite.py @@ -7,7 +7,7 @@ import argparse from migen import * -from litex_boards.community.platforms import de10lite +from litex_boards.platforms import de10lite from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * diff --git a/litex_boards/community/targets/de1soc.py b/litex_boards/community/targets/de1soc.py index 254b0c7..455521f 100755 --- a/litex_boards/community/targets/de1soc.py +++ b/litex_boards/community/targets/de1soc.py @@ -7,7 +7,7 @@ import argparse from migen import * -from litex_boards.community.platforms import de1soc +from litex_boards.platforms import de1soc from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * diff --git a/litex_boards/community/targets/de2_115.py b/litex_boards/community/targets/de2_115.py index a9c7d51..3d82159 100755 --- a/litex_boards/community/targets/de2_115.py +++ b/litex_boards/community/targets/de2_115.py @@ -7,7 +7,7 @@ import argparse from migen import * -from litex_boards.community.platforms import de2_115 +from litex_boards.platforms import de2_115 from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * diff --git a/litex_boards/community/targets/ecp5_evn.py b/litex_boards/community/targets/ecp5_evn.py index a276855..6c72e59 100755 --- a/litex_boards/community/targets/ecp5_evn.py +++ b/litex_boards/community/targets/ecp5_evn.py @@ -8,7 +8,7 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.community.platforms import ecp5_evn +from litex_boards.platforms import ecp5_evn from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * diff --git a/litex_boards/official/targets/arty.py b/litex_boards/official/targets/arty.py index 184186f..f2ddd7b 100755 --- a/litex_boards/official/targets/arty.py +++ b/litex_boards/official/targets/arty.py @@ -7,7 +7,7 @@ import argparse from migen import * -from litex_boards.official.platforms import arty +from litex_boards.platforms import arty from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * diff --git a/litex_boards/official/targets/de0nano.py b/litex_boards/official/targets/de0nano.py index 5b635b0..82ce414 100755 --- a/litex_boards/official/targets/de0nano.py +++ b/litex_boards/official/targets/de0nano.py @@ -7,7 +7,7 @@ import argparse from migen import * -from litex_boards.official.platforms import de0nano +from litex_boards.platforms import de0nano from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * diff --git a/litex_boards/official/targets/genesys2.py b/litex_boards/official/targets/genesys2.py index c1390ff..ac3c27b 100755 --- a/litex_boards/official/targets/genesys2.py +++ b/litex_boards/official/targets/genesys2.py @@ -7,7 +7,7 @@ import argparse from migen import * -from litex_boards.official.platforms import genesys2 +from litex_boards.platforms import genesys2 from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * diff --git a/litex_boards/official/targets/kc705.py b/litex_boards/official/targets/kc705.py index 622d8e4..1579f01 100755 --- a/litex_boards/official/targets/kc705.py +++ b/litex_boards/official/targets/kc705.py @@ -9,7 +9,7 @@ import argparse from migen import * -from litex_boards.official.platforms import kc705 +from litex_boards.platforms import kc705 from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * diff --git a/litex_boards/official/targets/kcu105.py b/litex_boards/official/targets/kcu105.py index 7a5a638..44194c8 100755 --- a/litex_boards/official/targets/kcu105.py +++ b/litex_boards/official/targets/kcu105.py @@ -7,7 +7,7 @@ import argparse from migen import * -from litex_boards.official.platforms import kcu105 +from litex_boards.platforms import kcu105 from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * diff --git a/litex_boards/official/targets/minispartan6.py b/litex_boards/official/targets/minispartan6.py index 7d0d96f..5045ff4 100755 --- a/litex_boards/official/targets/minispartan6.py +++ b/litex_boards/official/targets/minispartan6.py @@ -11,7 +11,7 @@ from fractions import Fraction from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.official.platforms import minispartan6 +from litex_boards.platforms import minispartan6 from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * diff --git a/litex_boards/official/targets/nexys4ddr.py b/litex_boards/official/targets/nexys4ddr.py index 1eeef49..994a5c8 100755 --- a/litex_boards/official/targets/nexys4ddr.py +++ b/litex_boards/official/targets/nexys4ddr.py @@ -7,7 +7,7 @@ import argparse from migen import * -from litex_boards.official.platforms import nexys4ddr +from litex_boards.platforms import nexys4ddr from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * diff --git a/litex_boards/official/targets/nexys_video.py b/litex_boards/official/targets/nexys_video.py index d80d9b8..4805056 100755 --- a/litex_boards/official/targets/nexys_video.py +++ b/litex_boards/official/targets/nexys_video.py @@ -7,7 +7,7 @@ import argparse from migen import * -from litex_boards.official.platforms import nexys_video +from litex_boards.platforms import nexys_video from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * diff --git a/litex_boards/official/targets/versa_ecp5.py b/litex_boards/official/targets/versa_ecp5.py index 5dc8a57..d70dd5e 100755 --- a/litex_boards/official/targets/versa_ecp5.py +++ b/litex_boards/official/targets/versa_ecp5.py @@ -9,7 +9,7 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.official.platforms import versa_ecp5 +from litex_boards.platforms import versa_ecp5 from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * diff --git a/litex_boards/partner/targets/netv2.py b/litex_boards/partner/targets/netv2.py index adea646..6885916 100755 --- a/litex_boards/partner/targets/netv2.py +++ b/litex_boards/partner/targets/netv2.py @@ -7,7 +7,7 @@ import argparse from migen import * -from litex_boards.partner.platforms import netv2 +from litex_boards.platforms import netv2 from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * diff --git a/litex_boards/partner/targets/trellisboard.py b/litex_boards/partner/targets/trellisboard.py index 4a85631..f15b0d6 100755 --- a/litex_boards/partner/targets/trellisboard.py +++ b/litex_boards/partner/targets/trellisboard.py @@ -8,7 +8,7 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.partner.platforms import trellisboard +from litex_boards.platforms import trellisboard from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * diff --git a/litex_boards/partner/targets/ulx3s.py b/litex_boards/partner/targets/ulx3s.py index b126e9a..db416cc 100755 --- a/litex_boards/partner/targets/ulx3s.py +++ b/litex_boards/partner/targets/ulx3s.py @@ -9,7 +9,7 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.partner.platforms import ulx3s +from litex_boards.platforms import ulx3s from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import *