From ae47172d2acef2a5fabd6204277675ca540d31b4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 14 Nov 2022 10:20:12 +0100 Subject: [PATCH] targets/decklink_mini_4k: Update clock constraints. --- litex_boards/targets/decklink_mini_4k.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/decklink_mini_4k.py b/litex_boards/targets/decklink_mini_4k.py index 292819f..632a697 100755 --- a/litex_boards/targets/decklink_mini_4k.py +++ b/litex_boards/targets/decklink_mini_4k.py @@ -46,7 +46,7 @@ class _CRG(LiteXModule): # Clk. clk100 = platform.request("clk100") platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk100_IBUF]") - platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets main_s7pll0_clkin]") + platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets s7pll0_clkin]") # Main PLL. self.pll = pll = S7PLL(speedgrade=-1)