From ae5494d7b62e539732428a6083dc158ea3bf9530 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 8 Jan 2021 19:00:58 +0100 Subject: [PATCH] orangecrab: defaults to USB-ACM UART. --- litex_boards/targets/orangecrab.py | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 6a7c272..fd5f5a1 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -150,12 +150,11 @@ class BaseSoC(SoCCore): platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain) # Serial ----------------------------------------------------------------------------------- - if kwargs["uart_name"] == "usb_acm": - # FIXME: do proper install of ValentyUSB. + if kwargs["uart_name"] in ["serial", "usb_acm"]: + kwargs["uart_name"] = "usb_acm" + # Defaults to USB ACM through ValentyUSB. os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri") sys.path.append("valentyusb") - else: - platform.add_extension(orangecrab.feather_serial) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq,