From aef78831c8ba177856b2bd1af05c92ac33fb13bc Mon Sep 17 00:00:00 2001 From: Kaz Kojima Date: Wed, 27 Jan 2021 18:19:27 +0900 Subject: [PATCH] colorlight_i5: Use tx_delay=0 for LiteEthPHYRGMII instead of target specifig bios initialization --- litex_boards/targets/colorlight_i5.py | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/litex_boards/targets/colorlight_i5.py b/litex_boards/targets/colorlight_i5.py index 1d89583..450e370 100755 --- a/litex_boards/targets/colorlight_i5.py +++ b/litex_boards/targets/colorlight_i5.py @@ -149,9 +149,9 @@ class BaseSoC(SoCCore): if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks", eth_phy), - pads = self.platform.request("eth", eth_phy)) + pads = self.platform.request("eth", eth_phy), + tx_delay = 0) self.add_csr("ethphy") - self.add_constant("TARGET_BIOS_INIT", 1) if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: @@ -223,13 +223,6 @@ def main(): soc.add_sdcard() builder = Builder(soc, **builder_argdict(args)) - if args.with_ethernet: - os.makedirs(os.path.join(builder.software_dir, "include/generated"), - exist_ok=True) - write_to_file( - os.path.join(builder.software_dir, "include/generated", "target.h"), - "// Colorlight i5 needs this to disable TX data to clock delay.\n" - "#define TARGET_BIOS_INIT_FUNC() mdio_write(0, 0x1c, 0x8c00)") builder.build(**trellis_argdict(args), run=args.build)