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adding colognechip_gatemate_evb

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Gwenhael Goavec-Merou 2022-06-13 22:04:23 +02:00 committed by Gwenhael Goavec-Merou
parent 33a0975dd7
commit af09c81db6
3 changed files with 240 additions and 0 deletions
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141
litex_boards/platforms/colognechip_gatemate_evb.py Normal file
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#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2023 Gwenhael Goavec-merou<gwenhael.goavec-merou@trabucayre.com>
# SPDX-License-Identifier: BSD-2-Clause
# Board documentation/schematics:
# https://colognechip.com/docs/ds1003-gatemate1-evalboard-3v1-latest.pdf
from litex.build.generic_platform import *
from litex.build.colognechip.platform import CologneChipPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk10", 0, Pins("IO_SB_A8"), Misc("SCHMITT_TRIGGER=true")),
# Leds
("user_led_n", 0, Pins("IO_EB_B1")),
("user_led_n", 1, Pins("IO_EB_B2")),
("user_led_n", 2, Pins("IO_EB_B3")),
("user_led_n", 3, Pins("IO_EB_B4")),
("user_led_n", 4, Pins("IO_EB_B5")),
("user_led_n", 5, Pins("IO_EB_B6")),
("user_led_n", 6, Pins("IO_EB_B7")),
("user_led_n", 7, Pins("IO_EB_B8")),
# Button
("user_btn_n", 0, Pins("IO_EB_B0")),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("IO_WA_A8")),
Subsignal("clk", Pins("IO_WA_B8")),
Subsignal("miso", Pins("IO_WA_B7")),
Subsignal("mosi", Pins("IO_WA_A7")),
Subsignal("wp", Pins("IO_WA_B6")),
Subsignal("hold", Pins("IO_WA_B6")),
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("IO_WA_A8")),
Subsignal("clk", Pins("IO_WA_B8")),
Subsignal("dq", Pins("IO_WA_B7 IO_WA_A7 IO_WA_B6 IO_WA_B6")),
),
# HyperRAM
("hyperram", 0,
Subsignal("dq", Pins("IO_WB_A5 IO_WB_B5 IO_WB_A6 IO_WB_B6 IO_WB_A7 IO_WB_B7 IO_WB_A8 IO_WB_B8")),
Subsignal("rwds", Pins("IO_WB_B4")),
Subsignal("cs_n", Pins("IO_WB_B0")),
Subsignal("rst_n", Pins("IO_WB_A2")),
Subsignal("clk_p", Pins("IO_WB_A3")),
Subsignal("clk_n", Pins("IO_WB_B3")),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("PMODA", "IO_NB_A0 IO_NB_A1 IO_NB_A2 IO_NB_A3 IO_NB_B0 IO_NB_B1 IO_NB_B2 IO_NB_B3"),
("PMODB", "IO_NB_A4 IO_NB_A5 IO_NB_A6 IO_NB_A7 IO_NB_B4 IO_NB_B5 IO_NB_B6 IO_NB_B7"),
("io_na", "IO_NA_A0 IO_NA_B0",
"IO_NA_A1 IO_NA_B1",
"IO_NA_A2 IO_NA_B2",
"IO_NA_A3 IO_NA_B3",
"IO_NA_A4 IO_NA_B4",
"IO_NA_A5 IO_NA_B5",
"IO_NA_A6 IO_NA_B6",
"IO_NA_A7 IO_NA_B7",
"IO_NA_A8 IO_NA_B8"),
("io_nb", "IO_NB_A4 IO_NB_A5",
"IO_NB_A6 IO_NB_A7",
"IO_NB_B4 IO_NB_B5",
"IO_NB_B6 IO_NB_B7"),
("io_ea", "IO_EA_A0 IO_EA_B0",
"IO_EA_A1 IO_EA_B1",
"IO_EA_A2 IO_EA_B2",
"IO_EA_A3 IO_EA_B3",
"IO_EA_A4 IO_EA_B4",
"IO_EA_A5 IO_EA_B5",
"IO_EA_A6 IO_EA_B6",
"IO_EA_A7 IO_EA_B7",
"IO_EA_A8 IO_EA_B8"),
("io_sa", "IO_SA_A0 IO_SA_B0",
"IO_SA_A1 IO_SA_B1",
"IO_SA_A2 IO_SA_B2",
"IO_SA_A3 IO_SA_B3",
"IO_SA_A4 IO_SA_B4",
"IO_SA_A5 IO_SA_B5",
"IO_SA_A6 IO_SA_B6",
"IO_SA_A7 IO_SA_B7",
"IO_SA_A8 IO_SA_B8"),
("io_sb", "IO_SB_A0 IO_SB_B0",
"IO_SB_A1 IO_SB_B1",
"IO_SB_A2 IO_SB_B2",
"IO_SB_A3 IO_SB_B3",
"IO_SB_A4 IO_SB_B4",
"IO_SB_A5 IO_SB_B5",
"IO_SB_A6 IO_SB_B6",
"IO_SB_A7 IO_SB_B7",
"IO_SB_A8 IO_SB_B8"),
("io_wc", "IO_WC_A0 IO_WC_B0",
"IO_WC_A1 IO_WC_B1",
"IO_WC_A2 IO_WC_B2",
"IO_WC_A3 IO_WC_B3",
"IO_WC_A4 IO_WC_B4",
"IO_WC_A5 IO_WC_B5",
"IO_WC_A6 IO_WC_B6",
"IO_WC_A7 IO_WC_B7",
"IO_WC_A8 IO_WC_B8"),
]
# PMODS --------------------------------------------------------------------------------------------
def usb_pmod_io(pmod):
return [
# USB-UART PMOD: https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/
("usb_uart", 0,
Subsignal("tx", Pins(f"{pmod}:1")),
Subsignal("rx", Pins(f"{pmod}:2")),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(CologneChipPlatform):
default_clk_name = "clk10"
default_clk_period = 1e9/10e6
def __init__(self, toolchain="colognechip"):
CologneChipPlatform.__init__(self, "CCGM1A1", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return OpenFPGALoader("gatemate_evb_jtag")
def do_finalize(self, fragment):
CologneChipPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk10", loose=True), 1e9/10e6)

97
litex_boards/targets/colognechip_gatemate_evb.py Executable file
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#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2023 Gwenhael Goavec-merou<gwenhael.goavec-merou@trabucayre.com>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.gen import *
from litex_boards.platforms import colognechip_gatemate_evb
from litex.build.io import CRG
from litex.soc.cores.clock.colognechip import GateMatePLL
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.build.generic_platform import Pins
from litex.soc.cores.led import LedChaser
# CRG ----------------------------------------------------------------------------------------------
class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
rst_n = Signal()
self.cd_sys = ClockDomain()
# # #
# Clk / Rst
clk10 = platform.request("clk10")
self.rst = ~platform.request("user_btn_n", 0)
self.specials += Instance("CC_USR_RSTN", o_USR_RSTN = rst_n)
# PLL
self.pll = pll = GateMatePLL(perf_mode="economy")
self.comb += pll.reset.eq(~rst_n | self.rst)
pll.register_clkin(clk10, 10e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=48e6,
with_led_chaser = True,
**kwargs):
platform = colognechip_gatemate_evb.Platform()
# USBUART PMOD as Serial--------------------------------------------------------------------
platform.add_extension(colognechip_gatemate_evb.usb_pmod_io("PMODB"))
kwargs["uart_name"] = "usb_uart"
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on GateMate EVB", **kwargs)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
pads = platform.request_all("user_led_n"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=colognechip_gatemate_evb.Platform, description="LiteX SoC on Gatemate EVB")
parser.add_target_argument("--sys-clk-freq", default=24e6, type=float, help="System clock frequency.")
parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq,
**parser.soc_argdict)
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**parser.toolchain_argdict)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
from litex.build.openfpgaloader import OpenFPGALoader
prog = OpenFPGALoader("gatemate_evb_spi")
prog.flash(0, builder.get_bitstream_filename(mode="flash"))
if __name__ == "__main__":
main()

2
test/test_targets.py
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@ -19,6 +19,7 @@ class TestTargets(unittest.TestCase):
"qmtech_rp2040_daughterboard", # Reason: Not a real platform. "qmtech_rp2040_daughterboard", # Reason: Not a real platform.
"enclustra_st1", # Readon: Not a real platform. "enclustra_st1", # Readon: Not a real platform.
"quicklogic_quickfeather", # Reason: No default clock. "quicklogic_quickfeather", # Reason: No default clock.
"colognechip_gatemate_evb", # Reason: toolchain not yet mainlined
"efinix_titanium_ti60_f225_dev_kit", # Reason: Require Efinity toolchain. "efinix_titanium_ti60_f225_dev_kit", # Reason: Require Efinity toolchain.
"efinix_trion_t120_bga576_dev_kit", # Reason: Require Efinity toolchain. "efinix_trion_t120_bga576_dev_kit", # Reason: Require Efinity toolchain.
"efinix_trion_t20_bga256_dev_kit", # Reason: Require Efinity toolchain. "efinix_trion_t20_bga256_dev_kit", # Reason: Require Efinity toolchain.
@ -33,6 +34,7 @@ class TestTargets(unittest.TestCase):
excluded_targets = [ excluded_targets = [
"simple", # Reason: Generic target. "simple", # Reason: Generic target.
"quicklogic_quickfeather", # Reason: No default clock. "quicklogic_quickfeather", # Reason: No default clock.
"colognechip_gatemate_evb", # Reason: toolchain not yet mainlined
"efinix_titanium_ti60_f225_dev_kit", # Reason: Require Efinity toolchain. "efinix_titanium_ti60_f225_dev_kit", # Reason: Require Efinity toolchain.
"efinix_trion_t120_bga576_dev_kit", # Reason: Require Efinity toolchain. "efinix_trion_t120_bga576_dev_kit", # Reason: Require Efinity toolchain.
"efinix_trion_t20_bga256_dev_kit", # Reason: Require Efinity toolchain. "efinix_trion_t20_bga256_dev_kit", # Reason: Require Efinity toolchain.