From b01abce7d5279b1ba2c717fdf7381291715ff272 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Thu, 1 Jun 2023 16:45:33 -0400 Subject: [PATCH] platform/stlv7325-v2: update VCCIO to fix --with-pcie generation --- litex_boards/platforms/sitlinv_stlv7325_v2.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litex_boards/platforms/sitlinv_stlv7325_v2.py b/litex_boards/platforms/sitlinv_stlv7325_v2.py index f5b3f54..e325182 100644 --- a/litex_boards/platforms/sitlinv_stlv7325_v2.py +++ b/litex_boards/platforms/sitlinv_stlv7325_v2.py @@ -16,7 +16,7 @@ from litex.build.openocd import OpenOCD def _get_io(voltage="2.5V"): assert voltage in ["2.5V", "3.3V"] - VCCIO = str(25 if voltage == "2.5V" else 33) + VCCIO = {"2.5V": "25", "3.3V": "33"}[voltage] _io = [ # Clk / Rst ("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")), @@ -206,7 +206,7 @@ def _get_io(voltage="2.5V"): # PCIe ("pcie_x1", 0, - Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")), + Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS" + VCCIO)), Subsignal("clk_p", Pins("H6")), Subsignal("clk_n", Pins("H5")), Subsignal("rx_p", Pins("B6")), @@ -215,7 +215,7 @@ def _get_io(voltage="2.5V"): Subsignal("tx_n", Pins("A3")) ), ("pcie_x2", 0, - Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")), + Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS" + VCCIO)), Subsignal("clk_p", Pins("H6")), Subsignal("clk_n", Pins("H5")), Subsignal("rx_p", Pins("B6 C4")), @@ -224,7 +224,7 @@ def _get_io(voltage="2.5V"): Subsignal("tx_n", Pins("A3 B1")) ), ("pcie_x4", 0, - Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")), + Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS" + VCCIO)), Subsignal("clk_p", Pins("H6")), Subsignal("clk_n", Pins("H5")), Subsignal("rx_p", Pins("B6 C4 E4 G4")),