From b1107e94d4ff46bfd3241ef9de7f52ff591ffea4 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 16 Nov 2022 23:25:49 +0800 Subject: [PATCH] sitlinv_stlv7325: use S7PLL instead of S7MMCM for system clock As we do not need fine phase tweaking for the main system clock, use S7PLL instead of S7MMCM to allow higher VCO frequency and more flexible sys_clk_freq. Signed-off-by: Icenowy Zheng --- litex_boards/targets/sitlinv_stlv7325.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/sitlinv_stlv7325.py b/litex_boards/targets/sitlinv_stlv7325.py index c8e2650..5485b9c 100755 --- a/litex_boards/targets/sitlinv_stlv7325.py +++ b/litex_boards/targets/sitlinv_stlv7325.py @@ -47,7 +47,7 @@ class _CRG(LiteXModule): rst_n = platform.request("cpu_reset_n") # PLL. - self.pll = pll = S7MMCM(speedgrade=-2) + self.pll = pll = S7PLL(speedgrade=-2) self.comb += pll.reset.eq(~rst_n | self.rst) pll.register_clkin(clk200, 200e6) pll.create_clkout(self.cd_sys, sys_clk_freq)