From b2813cfb70317da798e420fd208167c608d7cca1 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Sat, 6 Nov 2021 08:45:03 +0700 Subject: [PATCH] use the right DRAM chip for the QMTech Altera boards --- litex_boards/targets/qmtech_10cl006.py | 4 ++-- litex_boards/targets/qmtech_5cefa2.py | 4 ++-- litex_boards/targets/qmtech_ep4ce15.py | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/litex_boards/targets/qmtech_10cl006.py b/litex_boards/targets/qmtech_10cl006.py index cab5013..92629da 100755 --- a/litex_boards/targets/qmtech_10cl006.py +++ b/litex_boards/targets/qmtech_10cl006.py @@ -21,7 +21,7 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser -from litedram.modules import IS42S16160 +from litedram.modules import W9825G6KH6 from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY from litex.soc.cores.video import VideoVGAPHY @@ -99,7 +99,7 @@ class BaseSoC(SoCCore): self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, - module = IS42S16160(sys_clk_freq, sdram_rate), + module = W9825G6KH6(sys_clk_freq, sdram_rate), l2_cache_size = kwargs.get("l2_size", 8192) ) diff --git a/litex_boards/targets/qmtech_5cefa2.py b/litex_boards/targets/qmtech_5cefa2.py index 58e6e50..b186d3e 100755 --- a/litex_boards/targets/qmtech_5cefa2.py +++ b/litex_boards/targets/qmtech_5cefa2.py @@ -22,7 +22,7 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser -from litedram.modules import IS42S16160 +from litedram.modules import W9825G6KH6 from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY from litex.soc.cores.video import VideoVGAPHY @@ -100,7 +100,7 @@ class BaseSoC(SoCCore): self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, - module = IS42S16160(sys_clk_freq, sdram_rate), + module = W9825G6KH6(sys_clk_freq, sdram_rate), l2_cache_size = kwargs.get("l2_size", 8192) ) diff --git a/litex_boards/targets/qmtech_ep4ce15.py b/litex_boards/targets/qmtech_ep4ce15.py index a91f2f4..f49a6ad 100755 --- a/litex_boards/targets/qmtech_ep4ce15.py +++ b/litex_boards/targets/qmtech_ep4ce15.py @@ -21,7 +21,7 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser -from litedram.modules import IS42S16160 +from litedram.modules import W9825G6KH6 from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY from litex.soc.cores.video import VideoVGAPHY @@ -97,7 +97,7 @@ class BaseSoC(SoCCore): self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, - module = IS42S16160(sys_clk_freq, sdram_rate), + module = W9825G6KH6(sys_clk_freq, sdram_rate), l2_cache_size = kwargs.get("l2_size", 8192) )