diff --git a/litex_boards/platforms/aliexpress_u420t.py b/litex_boards/platforms/aliexpress_u420t.py index 0578edc..ac58d83 100644 --- a/litex_boards/platforms/aliexpress_u420t.py +++ b/litex_boards/platforms/aliexpress_u420t.py @@ -1,11 +1,8 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2018-2019 Florent Kermarrec +# Copyright (c) 2022 Alex Petrov # SPDX-License-Identifier: BSD-2-Clause -# Kintex7-420T -# Part xc7k420tiffg901-2L v0.2 update -# ported by Alex Petrov aka sysman from litex.build.generic_platform import * from litex.build.xilinx import XilinxPlatform, VivadoProgrammer @@ -15,42 +12,33 @@ from litex.build.openocd import OpenOCD _io = [ # Clk / Rst - # u420t clk_y1 G27/ clk_y3 E25 - ("clk100", 0, Pins("G27"), IOStandard("LVCMOS33")), - #("sysclk", 0, Pins("E25"), IOStandard("LVCMOS33")), - #("clk100", 0, - # Subsignal("p", Pins("AB27"), IOStandard("DIFF_SSTL15")), - # Subsignal("n", Pins("AA27"), IOStandard("DIFF_SSTL15")) - #), + ("clk100", 0, Pins("G27"), IOStandard("LVCMOS33")), ("cpu_reset", 0, Pins("W12"), IOStandard("LVCMOS33")), - # Leds board: D3-D10 - ("user_led", 0, Pins("AJ22"), IOStandard("LVCMOS33")), - ("user_led", 1, Pins("AJ21"), IOStandard("LVCMOS33")), - ("user_led", 2, Pins("AK21"), IOStandard("LVCMOS33")), - ("user_led", 3, Pins("AK20"), IOStandard("LVCMOS33")), - ("user_led", 4, Pins("AK19"), IOStandard("LVCMOS33")), - ("user_led", 5, Pins("AJ19"), IOStandard("LVCMOS33")), - ("user_led", 6, Pins("AK18"), IOStandard("LVCMOS33")), - ("user_led", 7, Pins("AJ18"), IOStandard("LVCMOS33")), + # Leds + ("user_led", 0, Pins("AJ22"), IOStandard("LVCMOS33")), # D3 + ("user_led", 1, Pins("AJ21"), IOStandard("LVCMOS33")), # D4 + ("user_led", 2, Pins("AK21"), IOStandard("LVCMOS33")), # D5 + ("user_led", 3, Pins("AK20"), IOStandard("LVCMOS33")), # D6 + ("user_led", 4, Pins("AK19"), IOStandard("LVCMOS33")), # D7 + ("user_led", 5, Pins("AJ19"), IOStandard("LVCMOS33")), # D8 + ("user_led", 6, Pins("AK18"), IOStandard("LVCMOS33")), # D9 + ("user_led", 7, Pins("AJ18"), IOStandard("LVCMOS33")), # D10 # Buttons ("user_btn_k3", 0, Pins("AK15"), IOStandard("LVCMOS33")), ("user_btn_k2", 0, Pins("AK16"), IOStandard("LVCMOS33")), - # ("user_btnb", 0, Pins("AB11"), IOStandard("LVCMOS33")), - # http://www.wch-ic.com/products/CH340.html - # Serial CH340 , warning: wrong schema + # Serial (CH340) ("serial", 0, - Subsignal("tx", Pins("AK23")), ## U340 schem rx - Subsignal("rx", Pins("AJ23")), ## U340 schem tx + Subsignal("tx", Pins("AK23")), + Subsignal("rx", Pins("AJ23")), IOStandard("LVCMOS33") ), # SPIFlash (Micron N25Q256A (32MB)) ("spiflash", 0, Subsignal("cs_n", Pins("V26"), IOStandard("LVCMOS33")), - #Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")), Subsignal("mosi", Pins("R30"), IOStandard("LVCMOS33")), Subsignal("miso", Pins("T30"), IOStandard("LVCMOS33")), Subsignal("wp", Pins("R28"), IOStandard("LVCMOS33")), @@ -58,14 +46,13 @@ _io = [ ), ("spiflash4x", 0, Subsignal("cs_n", Pins("V26"), IOStandard("LVCMOS33")), - #Subsignal("clk", Pins("")), # driven through JTAG H13 #T22 ? Subsignal("dq", Pins("R30 T30 R28 T28"), IOStandard("LVCMOS33")) ), ] # Connectors --------------------------------------------------------------------------------------- -# to add connector + _connectors = [ # main board connector, pins as marked ( "main", { @@ -94,9 +81,6 @@ _connectors = [ }) ] -# PMODS -------------------------------------------------------------------------------------------- - - # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): @@ -105,9 +89,6 @@ class Platform(XilinxPlatform): def __init__(self, toolchain="vivado"): XilinxPlatform.__init__(self, "xc7k420tl-ffg901", _io, toolchain=toolchain) -# self.add_platform_command("") -# self.add_platform_command("set_property INTERNAL_VREF 0.900 [current_design]") -# self.add_platform_command("set_property INTERNAL_VREF 0.900 [get_iobanks 34]") def create_programmer(self): return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a420t.bit") diff --git a/litex_boards/targets/aliexpress_stlv7325.py b/litex_boards/targets/aliexpress_stlv7325.py old mode 100644 new mode 100755 index f39b639..ee8efdf --- a/litex_boards/targets/aliexpress_stlv7325.py +++ b/litex_boards/targets/aliexpress_stlv7325.py @@ -68,7 +68,7 @@ class BaseSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, - ident = "LiteX SoC on STLV7325", + ident = "LiteX SoC on AliExpress STLV7325", **kwargs) # CRG -------------------------------------------------------------------------------------- @@ -141,7 +141,7 @@ class BaseSoC(SoCCore): def main(): from litex.soc.integration.soc import LiteXSoCArgumentParser - parser = LiteXSoCArgumentParser(description="LiteX SoC on STLV7325") + parser = LiteXSoCArgumentParser(description="LiteX SoC on AliExpress STLV7325") target_group = parser.add_argument_group(title="Target options") target_group.add_argument("--build", action="store_true", help="Build bitstream.") target_group.add_argument("--load", action="store_true", help="Load bitstream.") diff --git a/litex_boards/targets/aliexpress_u420t.py b/litex_boards/targets/aliexpress_u420t.py old mode 100644 new mode 100755 index a8ecef1..d9c9118 --- a/litex_boards/targets/aliexpress_u420t.py +++ b/litex_boards/targets/aliexpress_u420t.py @@ -3,20 +3,17 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2020-2021 Xuanyu Hu +# Copyright (c) 2022 Alex Petrov # SPDX-License-Identifier: BSD-2-Clause -# ported by Alex Petrov aka sysman -# Kintex7-420T aliexpress -# Part xc7k420tiffg901-2L v0.2 from migen import * from litex_boards.platforms import u420t -from litex.soc.interconnect import wishbone -from litex.soc.cores.clock import * -from litex.soc.integration.soc import SoCRegion + from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * + +from litex.soc.cores.clock import * from litex.soc.cores.led import LedChaser # CRG ---------------------------------------------------------------------------------------------- @@ -24,26 +21,18 @@ from litex.soc.cores.led import LedChaser class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.rst = Signal() - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - self.clock_domains.cd_idelay = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() - # board is grade 2, but to fix halts use -1 - self.submodules.pll = pll = S7MMCM(speedgrade=-2) - ##self.submodules.pll = pll = S7MMCM(speedgrade=-1) - self.comb += pll.reset.eq(~platform.request("user_btn_k3") | self.rst) - pll.register_clkin(platform.request("clk100"), 100e6) - #workaround to bypass for clk100 error: No nets matched 'clk100' - #line:940 litex/litex/build/xilinx/vivado.py " [get_ports {clk}]", clk=clk) - ## platform.add_platform_command("create_clock -name clk100 -period 10.0 [get_ports clk100]") + # Clk / Rst. + clk100 = platform.request("clk100") + rst_n = platform.request("user_btn_k3") # FIXME: Why not cpu_reset? + + # PLL. + self.submodules.pll = pll = S7MMCM(speedgrade=-1) + self.comb += pll.reset.eq(~rst_n | self.rst) + pll.register_clkin(clk100, 100e6) pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) - pll.create_clkout(self.cd_idelay, 200e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. - # platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk100]") - # Reduce programming time - #self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]") - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ @@ -51,64 +40,43 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_spi_flash=False, **kwargs): platform = u420t.Platform() - # --- add more sram for riscv comfort - # xc7k420t BRAMs: 1670 (col length: RAMB18 160 RAMB36 80) - kwargs["integrated_rom_size"] = 0x8000 # 8kb - kwargs["integrated_sram_size"] = 0x10000 # 64kb - kwargs["integrated_main_ram_size"] = 0x40000 # 256kb ## change if needed - # SoCCore ----------------------------------_----------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, - ident = "LiteX SoC on u420t", + ident = "LiteX SoC on AliExpress u420t", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) - # Video ------------------------------------------------------------------------------------ - # no video - # no ram - # SPI Flash -------------------------------------------------------------------------------- + # SPI Flash -------------------------------------------------------------------------------- if with_spi_flash: from litespi.modules import N25Q256 from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="4x", module=W25Q256(Codes.READ_1_1_4)) - # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - # Add ROM linker region -------------------------------------------------------------------- - #self.bus.add_region("rom", SoCRegion( - # origin = self.bus.regions["spiflash"].origin + bios_flash_offset, - # size = 32*kB, - # linker = True) - #) - #self.cpu.set_reset_address(self.bus.regions["rom"].origin) - - # Build -------------------------------------------------------------------------------------------- def main(): from litex.soc.integration.soc import LiteXSoCArgumentParser - parser = LiteXSoCArgumentParser(description="LiteX SoC on u420t") + parser = LiteXSoCArgumentParser(description="LiteX SoC on AliExpress u420t") target_group = parser.add_argument_group(title="Target options") - target_group.add_argument("--build", action="store_true", help="Build bitstream.") - target_group.add_argument("--load", action="store_true", help="Load bitstream.") - target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") -# sdopts = target_group.add_mutually_exclusive_group() - sdopts.add_argument("--with-spi-flash", action="store_true", help="Enable SPI-mode flash support.") + target_group.add_argument("--build", action="store_true", help="Build bitstream.") + target_group.add_argument("--load", action="store_true", help="Load bitstream.") + target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") + target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI-mode flash support.") builder_args(parser) soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( - sys_clk_freq = int(float(args.sys_clk_freq)), + sys_clk_freq = int(float(args.sys_clk_freq)), **soc_core_argdict(args) ) -# soc.platform.add_extension(u420t._sdcard_pmod_io) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/alinx_ax7010.py b/litex_boards/targets/alinx_ax7010.py old mode 100644 new mode 100755