From b3175e4a9cf500e7f8bba3d9aacc374cc56f306a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 26 Nov 2021 16:20:44 +0100 Subject: [PATCH] fairwares_xtrx: Generate Fallback/Operational bitstreams. --- litex_boards/platforms/fairwaves_xtrx.py | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/litex_boards/platforms/fairwaves_xtrx.py b/litex_boards/platforms/fairwaves_xtrx.py index 8a36d1d..c8e4683 100644 --- a/litex_boards/platforms/fairwaves_xtrx.py +++ b/litex_boards/platforms/fairwaves_xtrx.py @@ -119,9 +119,21 @@ class Platform(XilinxPlatform): "set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]" ] - self.toolchain.additional_commands = \ - ["write_cfgmem -force -format bin -interface spix4 -size 16 " - "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] + self.toolchain.additional_commands = [ + # Non-Multiboot SPI-Flash bitstream generation. + "write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin", + + # Multiboot SPI-Flash Operational bitstream generation. + "set_property BITSTREAM.CONFIG.TIMER_CFG 0x0001fbd0 [current_design]", + "set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]", + "write_bitstream -force {build_name}_operational.bit ", + "write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}_operational.bit\" -file {build_name}_operational.bin", + + # Multiboot SPI-Flash Fallback bitstream generation. + "set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x00400000 [current_design]", + "write_bitstream -force {build_name}_fallback.bit ", + "write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}_fallback.bit\" -file {build_name}_fallback.bin" + ] def create_programmer(self): return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a50t.bit")