diff --git a/litex_boards/targets/adi_adrv2crr_fmc.py b/litex_boards/targets/adi_adrv2crr_fmc.py index 01100c9..7e608ba 100755 --- a/litex_boards/targets/adi_adrv2crr_fmc.py +++ b/litex_boards/targets/adi_adrv2crr_fmc.py @@ -47,10 +47,10 @@ class CRG(Module): platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [ - Instance("BUFGCE_DIV", name="main_bufgce_div", + Instance("BUFGCE_DIV", p_BUFGCE_DIVIDE=4, i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), - Instance("BUFGCE", name="main_bufgce", + Instance("BUFGCE", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), ] diff --git a/litex_boards/targets/avnet_aesku40.py b/litex_boards/targets/avnet_aesku40.py index f24768b..95ced1f 100755 --- a/litex_boards/targets/avnet_aesku40.py +++ b/litex_boards/targets/avnet_aesku40.py @@ -45,10 +45,10 @@ class _CRG(Module): platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [ - Instance("BUFGCE_DIV", name="main_bufgce_div", + Instance("BUFGCE_DIV", p_BUFGCE_DIVIDE=4, i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), - Instance("BUFGCE", name="main_bufgce", + Instance("BUFGCE", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), ] diff --git a/litex_boards/targets/decklink_quad_hdmi_recorder.py b/litex_boards/targets/decklink_quad_hdmi_recorder.py index 464f12d..b262cc5 100755 --- a/litex_boards/targets/decklink_quad_hdmi_recorder.py +++ b/litex_boards/targets/decklink_quad_hdmi_recorder.py @@ -47,10 +47,10 @@ class _CRG(Module): pll.create_clkout(self.cd_idelay, 200e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [ - Instance("BUFGCE_DIV", name="main_bufgce_div", + Instance("BUFGCE_DIV", p_BUFGCE_DIVIDE=4, i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), - Instance("BUFGCE", name="main_bufgce", + Instance("BUFGCE", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), ] self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys) diff --git a/litex_boards/targets/enclustra_mercury_xu5.py b/litex_boards/targets/enclustra_mercury_xu5.py index e73689e..2e5feaa 100755 --- a/litex_boards/targets/enclustra_mercury_xu5.py +++ b/litex_boards/targets/enclustra_mercury_xu5.py @@ -39,10 +39,10 @@ class _CRG(Module): platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [ - Instance("BUFGCE_DIV", name="main_bufgce_div", + Instance("BUFGCE_DIV", p_BUFGCE_DIVIDE=4, i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), - Instance("BUFGCE", name="main_bufgce", + Instance("BUFGCE", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), ] diff --git a/litex_boards/targets/sqrl_xcu1525.py b/litex_boards/targets/sqrl_xcu1525.py index 64e9798..ee4c0c7 100755 --- a/litex_boards/targets/sqrl_xcu1525.py +++ b/litex_boards/targets/sqrl_xcu1525.py @@ -44,10 +44,10 @@ class _CRG(Module): platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [ - Instance("BUFGCE_DIV", name="main_bufgce_div", + Instance("BUFGCE_DIV", p_BUFGCE_DIVIDE=4, i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), - Instance("BUFGCE", name="main_bufgce", + Instance("BUFGCE", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), ] diff --git a/litex_boards/targets/xilinx_alveo_u250.py b/litex_boards/targets/xilinx_alveo_u250.py index cc36733..39502e2 100755 --- a/litex_boards/targets/xilinx_alveo_u250.py +++ b/litex_boards/targets/xilinx_alveo_u250.py @@ -46,10 +46,10 @@ class _CRG(Module): platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [ - Instance("BUFGCE_DIV", name="main_bufgce_div", + Instance("BUFGCE_DIV", p_BUFGCE_DIVIDE=4, i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), - Instance("BUFGCE", name="main_bufgce", + Instance("BUFGCE", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), ] diff --git a/litex_boards/targets/xilinx_alveo_u280.py b/litex_boards/targets/xilinx_alveo_u280.py index 8efad68..772fb7b 100755 --- a/litex_boards/targets/xilinx_alveo_u280.py +++ b/litex_boards/targets/xilinx_alveo_u280.py @@ -72,10 +72,10 @@ class _CRG(Module): platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [ - Instance("BUFGCE_DIV", name="main_bufgce_div", + Instance("BUFGCE_DIV", p_BUFGCE_DIVIDE=4, i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), - Instance("BUFGCE", name="main_bufgce", + Instance("BUFGCE", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), # AsyncResetSynchronizer(self.cd_idelay, ~pll.locked), ] diff --git a/litex_boards/targets/xilinx_kcu105.py b/litex_boards/targets/xilinx_kcu105.py index 20f917a..e7f99e8 100755 --- a/litex_boards/targets/xilinx_kcu105.py +++ b/litex_boards/targets/xilinx_kcu105.py @@ -48,10 +48,10 @@ class _CRG(Module): platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [ - Instance("BUFGCE_DIV", name="main_bufgce_div", + Instance("BUFGCE_DIV", p_BUFGCE_DIVIDE=4, i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), - Instance("BUFGCE", name="main_bufgce", + Instance("BUFGCE", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), ] diff --git a/litex_boards/targets/xilinx_vcu118.py b/litex_boards/targets/xilinx_vcu118.py index 7b980ec..503e9ad 100755 --- a/litex_boards/targets/xilinx_vcu118.py +++ b/litex_boards/targets/xilinx_vcu118.py @@ -40,10 +40,10 @@ class _CRG(Module): platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [ - Instance("BUFGCE_DIV", name="main_bufgce_div", + Instance("BUFGCE_DIV", p_BUFGCE_DIVIDE=4, i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), - Instance("BUFGCE", name="main_bufgce", + Instance("BUFGCE", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), ] diff --git a/litex_boards/targets/xilinx_zcu104.py b/litex_boards/targets/xilinx_zcu104.py index a1424e2..aab7616 100755 --- a/litex_boards/targets/xilinx_zcu104.py +++ b/litex_boards/targets/xilinx_zcu104.py @@ -41,10 +41,10 @@ class _CRG(Module): platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [ - Instance("BUFGCE_DIV", name="main_bufgce_div", + Instance("BUFGCE_DIV", p_BUFGCE_DIVIDE=4, i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), - Instance("BUFGCE", name="main_bufgce", + Instance("BUFGCE", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), ] diff --git a/litex_boards/targets/xilinx_zcu106.py b/litex_boards/targets/xilinx_zcu106.py index b8f6650..14f0803 100755 --- a/litex_boards/targets/xilinx_zcu106.py +++ b/litex_boards/targets/xilinx_zcu106.py @@ -45,10 +45,10 @@ class _CRG(Module): platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [ - Instance("BUFGCE_DIV", name="main_bufgce_div", + Instance("BUFGCE_DIV", p_BUFGCE_DIVIDE=4, i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), - Instance("BUFGCE", name="main_bufgce", + Instance("BUFGCE", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), ]