From b53b79821e757a92ed9b7f15d7ebe5ad7a0bbd44 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 14 Feb 2022 11:35:08 +0100 Subject: [PATCH] platforms: Expose toolchain parameter on all platforms to ease switching to alternative/open-source toolchains. --- litex_boards/platforms/alchitry_au.py | 4 ++-- litex_boards/platforms/alchitry_mojo.py | 4 ++-- litex_boards/platforms/alinx_axu2cga.py | 4 ++-- .../antmicro_datacenter_ddr4_test_board.py | 4 ++-- .../platforms/antmicro_lpddr4_test_board.py | 4 ++-- litex_boards/platforms/avalanche.py | 4 ++-- litex_boards/platforms/berkeleylab_marble.py | 4 ++-- litex_boards/platforms/berkeleylab_marblemini.py | 4 ++-- .../platforms/decklink_intensity_pro_4k.py | 4 ++-- litex_boards/platforms/decklink_mini_4k.py | 4 ++-- .../platforms/decklink_quad_hdmi_recorder.py | 4 ++-- litex_boards/platforms/digilent_arty_s7.py | 4 ++-- litex_boards/platforms/digilent_arty_z7.py | 11 ++++------- litex_boards/platforms/digilent_atlys.py | 14 +++++++------- litex_boards/platforms/digilent_basys3.py | 4 ++-- litex_boards/platforms/digilent_cmod_a7.py | 4 ++-- litex_boards/platforms/digilent_genesys2.py | 4 ++-- litex_boards/platforms/digilent_nexys4.py | 4 ++-- litex_boards/platforms/digilent_nexys4ddr.py | 4 ++-- litex_boards/platforms/digilent_pynq_z1.py | 4 ++-- litex_boards/platforms/digilent_zedboard.py | 9 ++++----- litex_boards/platforms/digilent_zybo_z7.py | 4 ++-- litex_boards/platforms/ebaz4205.py | 4 ++-- .../platforms/efinix_titanium_ti60_f225_dev_kit.py | 4 ++-- .../platforms/efinix_trion_t120_bga576_dev_kit.py | 4 ++-- .../platforms/efinix_trion_t20_bga256_dev_kit.py | 4 ++-- .../platforms/efinix_trion_t20_mipi_dev_kit.py | 4 ++-- litex_boards/platforms/efinix_xyloni_dev_kit.py | 4 ++-- litex_boards/platforms/ego1.py | 4 ++-- litex_boards/platforms/enclustra_mercury_kx2.py | 4 ++-- litex_boards/platforms/enclustra_mercury_xu5.py | 4 ++-- litex_boards/platforms/fairwaves_xtrx.py | 4 ++-- .../platforms/jungle_electronics_fireant.py | 4 ++-- litex_boards/platforms/kosagi_netv2.py | 4 ++-- litex_boards/platforms/krtkl_snickerdoodle.py | 4 ++-- litex_boards/platforms/lattice_ice40up5k_evn.py | 5 ++--- litex_boards/platforms/lattice_machxo3.py | 4 ++-- litex_boards/platforms/linsn_rv901t.py | 4 ++-- litex_boards/platforms/logicbone.py | 2 +- litex_boards/platforms/marble.py | 4 ++-- litex_boards/platforms/marblemini.py | 4 ++-- litex_boards/platforms/micronova_mercury2.py | 4 ++-- litex_boards/platforms/mist.py | 4 ++-- litex_boards/platforms/mnt_rkx7.py | 4 ++-- litex_boards/platforms/myminieye_runber.py | 4 ++-- litex_boards/platforms/numato_aller.py | 4 ++-- litex_boards/platforms/numato_mimas_a7.py | 4 ++-- litex_boards/platforms/numato_tagus.py | 4 ++-- litex_boards/platforms/pano_logic_g2.py | 4 ++-- litex_boards/platforms/qmtech_10cl006.py | 4 ++-- litex_boards/platforms/qmtech_5cefa2.py | 4 ++-- litex_boards/platforms/qmtech_ep4cex5.py | 4 ++-- litex_boards/platforms/qmtech_wukong.py | 4 ++-- litex_boards/platforms/quicklogic_quickfeather.py | 4 ++-- litex_boards/platforms/redpitaya.py | 4 ++-- litex_boards/platforms/rz_easyfpga.py | 4 ++-- litex_boards/platforms/saanlima_pipistrello.py | 4 ++-- .../platforms/scarabhardware_minispartan6.py | 4 ++-- .../seeedstudio_spartan_edge_accelerator.py | 4 ++-- litex_boards/platforms/siglent_sds1104xe.py | 4 ++-- litex_boards/platforms/sipeed_tang_nano.py | 6 +++--- litex_boards/platforms/sipeed_tang_nano_4k.py | 4 ++-- litex_boards/platforms/sipeed_tang_nano_9k.py | 4 ++-- litex_boards/platforms/sipeed_tang_primer.py | 4 ++-- litex_boards/platforms/sqrl_acorn.py | 4 ++-- litex_boards/platforms/sqrl_fk33.py | 4 ++-- litex_boards/platforms/sqrl_xcu1525.py | 4 ++-- litex_boards/platforms/terasic_de0nano.py | 4 ++-- litex_boards/platforms/terasic_de10lite.py | 4 ++-- litex_boards/platforms/terasic_de10nano.py | 4 ++-- litex_boards/platforms/terasic_de1soc.py | 4 ++-- litex_boards/platforms/terasic_de2_115.py | 4 ++-- litex_boards/platforms/terasic_deca.py | 4 ++-- litex_boards/platforms/terasic_sockit.py | 4 ++-- litex_boards/platforms/trenz_c10lprefkit.py | 4 ++-- litex_boards/platforms/trenz_cyc1000.py | 4 ++-- litex_boards/platforms/trenz_max1000.py | 4 ++-- litex_boards/platforms/trenz_te0725.py | 4 ++-- litex_boards/platforms/trenz_tec0117.py | 4 ++-- litex_boards/platforms/tul_pynq_z2.py | 4 ++-- litex_boards/platforms/xilinx_ac701.py | 4 ++-- litex_boards/platforms/xilinx_alveo_u250.py | 4 ++-- litex_boards/platforms/xilinx_alveo_u280.py | 4 ++-- litex_boards/platforms/xilinx_kc705.py | 4 ++-- litex_boards/platforms/xilinx_kcu105.py | 4 ++-- litex_boards/platforms/xilinx_kv260.py | 4 ++-- litex_boards/platforms/xilinx_sp605.py | 4 ++-- litex_boards/platforms/xilinx_vc707.py | 4 ++-- litex_boards/platforms/xilinx_vcu118.py | 2 +- litex_boards/platforms/xilinx_zcu104.py | 4 ++-- litex_boards/platforms/xilinx_zcu106.py | 4 ++-- litex_boards/platforms/ztex213.py | 4 ++-- 92 files changed, 192 insertions(+), 197 deletions(-) diff --git a/litex_boards/platforms/alchitry_au.py b/litex_boards/platforms/alchitry_au.py index c7cd102..7fd548b 100644 --- a/litex_boards/platforms/alchitry_au.py +++ b/litex_boards/platforms/alchitry_au.py @@ -99,13 +99,13 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self, variant="au"): + def __init__(self, variant="au", toolchain="vivado"): device = { "au": "xc7a35t-ftg256-1", "au+": "xc7a100t-ftg256-2", }[variant] - XilinxPlatform.__init__(self, device, _io, toolchain="vivado") + XilinxPlatform.__init__(self, device, _io, toolchain=toolchain) self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 15]") self.toolchain.bitstream_commands = [ diff --git a/litex_boards/platforms/alchitry_mojo.py b/litex_boards/platforms/alchitry_mojo.py index ab24065..b9a72e4 100644 --- a/litex_boards/platforms/alchitry_mojo.py +++ b/litex_boards/platforms/alchitry_mojo.py @@ -114,8 +114,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc6slx9-2-tqg144", _io) + def __init__(self, toolchain="ise"): + XilinxPlatform.__init__(self, "xc6slx9-2-tqg144", _io, toolchain=toolchain) self.toolchain.additional_commands = ["write_bitstream -force -bin_file {build_name}"] def do_finalize(self, fragment): diff --git a/litex_boards/platforms/alinx_axu2cga.py b/litex_boards/platforms/alinx_axu2cga.py index b621d29..351871b 100644 --- a/litex_boards/platforms/alinx_axu2cga.py +++ b/litex_boards/platforms/alinx_axu2cga.py @@ -122,8 +122,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk25" default_clk_period = 1e9/25e6 - def __init__(self): - XilinxPlatform.__init__(self, "xczu2cg-sfvc784-1-e", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xczu2cg-sfvc784-1-e", _io, _connectors, toolchain=toolchain) def create_programmer(self, cable): return OpenFPGALoader("axu2cga", cable) diff --git a/litex_boards/platforms/antmicro_datacenter_ddr4_test_board.py b/litex_boards/platforms/antmicro_datacenter_ddr4_test_board.py index 4e4809c..719096b 100644 --- a/litex_boards/platforms/antmicro_datacenter_ddr4_test_board.py +++ b/litex_boards/platforms/antmicro_datacenter_ddr4_test_board.py @@ -124,8 +124,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self, device="xc7k160tffg676-1"): - XilinxPlatform.__init__(self, device, _io, toolchain="vivado") + def __init__(self, device="xc7k160tffg676-1", toolchain="vivado"): + XilinxPlatform.__init__(self, device, _io, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = \ diff --git a/litex_boards/platforms/antmicro_lpddr4_test_board.py b/litex_boards/platforms/antmicro_lpddr4_test_board.py index 866ac30..b9bf5ec 100644 --- a/litex_boards/platforms/antmicro_lpddr4_test_board.py +++ b/litex_boards/platforms/antmicro_lpddr4_test_board.py @@ -98,8 +98,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self, device="xc7k70tfbg484-1"): - XilinxPlatform.__init__(self, device, _io, toolchain="vivado") + def __init__(self, device="xc7k70tfbg484-1", toolchain="vivado"): + XilinxPlatform.__init__(self, device, _io, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = \ diff --git a/litex_boards/platforms/avalanche.py b/litex_boards/platforms/avalanche.py index 1954511..b0414d9 100644 --- a/litex_boards/platforms/avalanche.py +++ b/litex_boards/platforms/avalanche.py @@ -99,8 +99,8 @@ class Platform(MicrosemiPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - def __init__(self): - MicrosemiPlatform.__init__(self, "MPF300TS_ES-FCG484-1", _io) + def __init__(self, toolchain="libero_soc_polarfire"): + MicrosemiPlatform.__init__(self, "MPF300TS_ES-FCG484-1", _io, toolchain=toolchain) def do_finalize(self, fragment): MicrosemiPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/berkeleylab_marble.py b/litex_boards/platforms/berkeleylab_marble.py index f85e299..e09086c 100644 --- a/litex_boards/platforms/berkeleylab_marble.py +++ b/litex_boards/platforms/berkeleylab_marble.py @@ -320,8 +320,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk125" default_clk_period = 1e9 / 125e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7k160t-ffg676-2", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7k160t-ffg676-2", _io, _connectors, toolchain=toolchain) self.toolchain.bitstream_commands = [ "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]" ] diff --git a/litex_boards/platforms/berkeleylab_marblemini.py b/litex_boards/platforms/berkeleylab_marblemini.py index 33c493c..60a1b2c 100644 --- a/litex_boards/platforms/berkeleylab_marblemini.py +++ b/litex_boards/platforms/berkeleylab_marblemini.py @@ -250,8 +250,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk20_vcxo" default_clk_period = 1e9/20e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a100t-2fgg484", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7a100t-2fgg484", _io, _connectors, toolchain=toolchain) self.toolchain.bitstream_commands = [ "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]" ] diff --git a/litex_boards/platforms/decklink_intensity_pro_4k.py b/litex_boards/platforms/decklink_intensity_pro_4k.py index 02d6239..9bba1d9 100644 --- a/litex_boards/platforms/decklink_intensity_pro_4k.py +++ b/litex_boards/platforms/decklink_intensity_pro_4k.py @@ -64,8 +64,8 @@ class Platform(XilinxPlatform): default_clk_name = "debug" # FIXME. default_clk_period = 1e9/100e6 # FIXME. - def __init__(self): - XilinxPlatform.__init__(self, "xc7k70t-fbg676-1", _io, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7k70t-fbg676-1", _io, toolchain=toolchain) def create_programmer(self): return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a70t.bit") diff --git a/litex_boards/platforms/decklink_mini_4k.py b/litex_boards/platforms/decklink_mini_4k.py index 9631646..4dec31d 100644 --- a/litex_boards/platforms/decklink_mini_4k.py +++ b/litex_boards/platforms/decklink_mini_4k.py @@ -129,8 +129,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a100t-fgg676-3", _io, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7a100t-fgg676-3", _io, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = \ diff --git a/litex_boards/platforms/decklink_quad_hdmi_recorder.py b/litex_boards/platforms/decklink_quad_hdmi_recorder.py index 77c9a0b..745cb9f 100644 --- a/litex_boards/platforms/decklink_quad_hdmi_recorder.py +++ b/litex_boards/platforms/decklink_quad_hdmi_recorder.py @@ -160,8 +160,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk200" default_clk_period = 1e9/200e6 - def __init__(self): - XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() diff --git a/litex_boards/platforms/digilent_arty_s7.py b/litex_boards/platforms/digilent_arty_s7.py index a2a6724..e7752b5 100644 --- a/litex_boards/platforms/digilent_arty_s7.py +++ b/litex_boards/platforms/digilent_arty_s7.py @@ -207,12 +207,12 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self, variant="s7-50"): + def __init__(self, variant="s7-50", toolchain="vivado"): device = { "s7-25": "xc7s25csga324-1", "s7-50": "xc7s50csga324-1" }[variant] - XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado") + XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = \ diff --git a/litex_boards/platforms/digilent_arty_z7.py b/litex_boards/platforms/digilent_arty_z7.py index e175358..e38b49d 100644 --- a/litex_boards/platforms/digilent_arty_z7.py +++ b/litex_boards/platforms/digilent_arty_z7.py @@ -221,8 +221,8 @@ _connectors = [ # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): - default_clk_name = "clk125" - default_clk_freq = 125e6 + default_clk_name = "clk125" + default_clk_period = 1e9/125e6 def __init__(self, variant="z7-20", toolchain="vivado"): device = { @@ -234,14 +234,11 @@ class Platform(XilinxPlatform): "z7-20": "arty_z7_20" }[variant] - XilinxPlatform.__init__(self, device, _io, _connectors, - toolchain=toolchain) - self.default_clk_period = 1e9 / self.default_clk_freq + XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain) def create_programmer(self): return OpenFPGALoader(self.board) def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) - self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True), - self.default_clk_period) + self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e6/125e6) diff --git a/litex_boards/platforms/digilent_atlys.py b/litex_boards/platforms/digilent_atlys.py index af73fc1..bbd5357 100644 --- a/litex_boards/platforms/digilent_atlys.py +++ b/litex_boards/platforms/digilent_atlys.py @@ -219,8 +219,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self,): - XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors) + def __init__(self, toolchain="ise"): + XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors, toolchain=toolchain) self.add_platform_command("""CONFIG VCCAUX="3.3";""") def create_programmer(self): @@ -228,8 +228,8 @@ class Platform(XilinxPlatform): def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) - self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) - self.add_period_constraint(self.lookup_request("hdmi_in:clk_p", 0, loose=True), 1e9/74.25e6) - self.add_period_constraint(self.lookup_request("hdmi_in:clk_p", 1, loose=True), 1e9/74.25e6) - self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/25e6) - self.add_period_constraint(self.lookup_request("fx2:ifclk", loose=True), 1e9/100e6) + self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) + self.add_period_constraint(self.lookup_request("hdmi_in:clk_p", 0, loose=True), 1e9/74.25e6) + self.add_period_constraint(self.lookup_request("hdmi_in:clk_p", 1, loose=True), 1e9/74.25e6) + self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/25e6) + self.add_period_constraint(self.lookup_request("fx2:ifclk", loose=True), 1e9/100e6) diff --git a/litex_boards/platforms/digilent_basys3.py b/litex_boards/platforms/digilent_basys3.py index 8398c14..daade20 100644 --- a/litex_boards/platforms/digilent_basys3.py +++ b/litex_boards/platforms/digilent_basys3.py @@ -121,8 +121,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a35t-CPG236-1", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7a35t-CPG236-1", _io, _connectors, toolchain=toolchain) def create_programmer(self): return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a35t.bit") diff --git a/litex_boards/platforms/digilent_cmod_a7.py b/litex_boards/platforms/digilent_cmod_a7.py index 964bdc0..04593e2 100644 --- a/litex_boards/platforms/digilent_cmod_a7.py +++ b/litex_boards/platforms/digilent_cmod_a7.py @@ -83,8 +83,8 @@ class Platform(XilinxPlatform): def __init__(self, variant="a7-35", toolchain="vivado"): device = { - "a7-35": "xc7a35tcpg236-1" - }[variant] + "a7-35": "xc7a35tcpg236-1" + }[variant] XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain) def create_programmer(self): diff --git a/litex_boards/platforms/digilent_genesys2.py b/litex_boards/platforms/digilent_genesys2.py index d1b127b..8e65e6e 100644 --- a/litex_boards/platforms/digilent_genesys2.py +++ b/litex_boards/platforms/digilent_genesys2.py @@ -157,8 +157,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk200" default_clk_period = 1e9/200e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain=toolchain) self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") def create_programmer(self): diff --git a/litex_boards/platforms/digilent_nexys4.py b/litex_boards/platforms/digilent_nexys4.py index c9d910f..ae8e525 100644 --- a/litex_boards/platforms/digilent_nexys4.py +++ b/litex_boards/platforms/digilent_nexys4.py @@ -219,8 +219,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, _connectors, toolchain=toolchain) self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") def create_programmer(self): diff --git a/litex_boards/platforms/digilent_nexys4ddr.py b/litex_boards/platforms/digilent_nexys4ddr.py index 5276c45..0f7ad4b 100644 --- a/litex_boards/platforms/digilent_nexys4ddr.py +++ b/litex_boards/platforms/digilent_nexys4ddr.py @@ -182,8 +182,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, _connectors, toolchain=toolchain) self.add_platform_command("set_property INTERNAL_VREF 0.900 [get_iobanks 34]") def create_programmer(self): diff --git a/litex_boards/platforms/digilent_pynq_z1.py b/litex_boards/platforms/digilent_pynq_z1.py index ffaa153..c6f2cf7 100644 --- a/litex_boards/platforms/digilent_pynq_z1.py +++ b/litex_boards/platforms/digilent_pynq_z1.py @@ -166,8 +166,8 @@ class Platform(XilinxPlatform): default_clk_name = "sysclk" default_clk_period = 1e9/125e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7z020-clg400-1", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7z020-clg400-1", _io, _connectors, toolchain=toolchain) self.add_extension(_ps7_io) self.add_extension(_hdmi_rx_io) self.add_extension(_hdmi_tx_io) diff --git a/litex_boards/platforms/digilent_zedboard.py b/litex_boards/platforms/digilent_zedboard.py index c2738ad..f4b2004 100644 --- a/litex_boards/platforms/digilent_zedboard.py +++ b/litex_boards/platforms/digilent_zedboard.py @@ -201,14 +201,13 @@ _connectors = [ # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): - default_clk_name = "clk100" - default_clk_period = 10.0 + default_clk_name = "clk100" + default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7z020clg484-1", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7z020clg484-1", _io, _connectors, toolchain=toolchains) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", ] - self.default_clk_freq = 1e9 / self.default_clk_period def create_programmer(self): return OpenOCD(config="board/digilent_zedboard.cfg") diff --git a/litex_boards/platforms/digilent_zybo_z7.py b/litex_boards/platforms/digilent_zybo_z7.py index 9fc135d..a948475 100644 --- a/litex_boards/platforms/digilent_zybo_z7.py +++ b/litex_boards/platforms/digilent_zybo_z7.py @@ -92,8 +92,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk125" default_clk_period = 1e9/125e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain=toolchain) self.add_extension(_ps7_io) self.add_extension(_usb_uart_pmod_io) diff --git a/litex_boards/platforms/ebaz4205.py b/litex_boards/platforms/ebaz4205.py index 68612d7..adc62d3 100644 --- a/litex_boards/platforms/ebaz4205.py +++ b/litex_boards/platforms/ebaz4205.py @@ -66,8 +66,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk33_333" default_clk_period = 1e9/33.333e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain=toolchain) self.add_extension(_ps7_io) def create_programmer(self): diff --git a/litex_boards/platforms/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/platforms/efinix_titanium_ti60_f225_dev_kit.py index fcfa732..ccf9d89 100644 --- a/litex_boards/platforms/efinix_titanium_ti60_f225_dev_kit.py +++ b/litex_boards/platforms/efinix_titanium_ti60_f225_dev_kit.py @@ -106,8 +106,8 @@ class Platform(EfinixPlatform): default_clk_name = "clk25" default_clk_period = 1e9/50e6 - def __init__(self): - EfinixPlatform.__init__(self, "Ti60F225C3", _io, _connectors, iobank_info=iobank_info, toolchain="efinity") + def __init__(self, toolchain="efinity"): + EfinixPlatform.__init__(self, "Ti60F225C3", _io, _connectors, iobank_info=iobank_info, toolchain=toolchain) def create_programmer(self): return EfinixProgrammer() diff --git a/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py b/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py index d916308..e488bb5 100644 --- a/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py +++ b/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py @@ -155,8 +155,8 @@ class Platform(EfinixPlatform): default_clk_name = "clk40" default_clk_period = 1e9/40e6 - def __init__(self): - EfinixPlatform.__init__(self, "T120F576I4", _io, _connectors, iobank_info=_bank_info, toolchain="efinity") + def __init__(self, toolchain="efinity"): + EfinixPlatform.__init__(self, "T120F576I4", _io, _connectors, iobank_info=_bank_info, toolchain=toolchain) def create_programmer(self): return EfinixProgrammer() diff --git a/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py b/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py index ab906a4..1599757 100644 --- a/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py +++ b/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py @@ -89,8 +89,8 @@ class Platform(EfinixPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - def __init__(self): - EfinixPlatform.__init__(self, "T20F256C4", _io, _connectors, iobank_info=_bank_info, toolchain="efinity") + def __init__(self, toolchain="efinity"): + EfinixPlatform.__init__(self, "T20F256C4", _io, _connectors, iobank_info=_bank_info, toolchain=toolchain) def create_programmer(self): return EfinixProgrammer() diff --git a/litex_boards/platforms/efinix_trion_t20_mipi_dev_kit.py b/litex_boards/platforms/efinix_trion_t20_mipi_dev_kit.py index 9932b1a..8746b3b 100644 --- a/litex_boards/platforms/efinix_trion_t20_mipi_dev_kit.py +++ b/litex_boards/platforms/efinix_trion_t20_mipi_dev_kit.py @@ -66,8 +66,8 @@ class Platform(EfinixPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - def __init__(self): - EfinixPlatform.__init__(self, "T20F169C4", _io, _connectors, iobank_info=_bank_info, toolchain="efinity") + def __init__(self, toolchain="efinity"): + EfinixPlatform.__init__(self, "T20F169C4", _io, _connectors, iobank_info=_bank_info, toolchain=toolchain) def create_programmer(self): return EfinixProgrammer() diff --git a/litex_boards/platforms/efinix_xyloni_dev_kit.py b/litex_boards/platforms/efinix_xyloni_dev_kit.py index 93b2979..350f09b 100644 --- a/litex_boards/platforms/efinix_xyloni_dev_kit.py +++ b/litex_boards/platforms/efinix_xyloni_dev_kit.py @@ -73,8 +73,8 @@ class Platform(EfinixPlatform): default_clk_name = "clk33" default_clk_period = 1e9/33.333e6 - def __init__(self): - EfinixPlatform.__init__(self, "T8F81C2", _io, _connectors, toolchain="efinity") + def __init__(self, toolchain="efinity"): + EfinixPlatform.__init__(self, "T8F81C2", _io, _connectors, toolchain=toolchain) def create_programmer(self): return OpenFPGALoader("xyloni_spi") diff --git a/litex_boards/platforms/ego1.py b/litex_boards/platforms/ego1.py index 379a856..d3f7eda 100644 --- a/litex_boards/platforms/ego1.py +++ b/litex_boards/platforms/ego1.py @@ -142,8 +142,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a35ticsg324-1L", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7a35ticsg324-1L", _io, _connectors, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = \ diff --git a/litex_boards/platforms/enclustra_mercury_kx2.py b/litex_boards/platforms/enclustra_mercury_kx2.py index c10cc3c..ad916ec 100644 --- a/litex_boards/platforms/enclustra_mercury_kx2.py +++ b/litex_boards/platforms/enclustra_mercury_kx2.py @@ -75,8 +75,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk200" default_clk_period = 1e9/200e6 - def __init__(self): - XilinxPlatform.__init__(self, " xc7k160tffg676-2", _io, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, " xc7k160tffg676-2", _io, toolchain=toolchain) def create_programmer(self): return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7k160t.bit") diff --git a/litex_boards/platforms/enclustra_mercury_xu5.py b/litex_boards/platforms/enclustra_mercury_xu5.py index 719ef24..80c4af1 100644 --- a/litex_boards/platforms/enclustra_mercury_xu5.py +++ b/litex_boards/platforms/enclustra_mercury_xu5.py @@ -88,8 +88,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xczu2eg-sfvc784-1-i", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xczu2eg-sfvc784-1-i", _io, _connectors, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() diff --git a/litex_boards/platforms/fairwaves_xtrx.py b/litex_boards/platforms/fairwaves_xtrx.py index 98a2400..fa241d7 100644 --- a/litex_boards/platforms/fairwaves_xtrx.py +++ b/litex_boards/platforms/fairwaves_xtrx.py @@ -111,8 +111,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk60" default_clk_period = 1e9/60e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a50tcpg236-2", _io, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7a50tcpg236-2", _io, toolchain=toolchain) self.toolchain.bitstream_commands = [ "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", diff --git a/litex_boards/platforms/jungle_electronics_fireant.py b/litex_boards/platforms/jungle_electronics_fireant.py index e6015f5..376463f 100644 --- a/litex_boards/platforms/jungle_electronics_fireant.py +++ b/litex_boards/platforms/jungle_electronics_fireant.py @@ -51,8 +51,8 @@ class Platform(EfinixPlatform): default_clk_name = "clk33" default_clk_period = 1e9/33.33e6 - def __init__(self): - EfinixPlatform.__init__(self, "T8F81C2", _io, _connectors, toolchain="efinity") + def __init__(self, toolchain="efinity"): + EfinixPlatform.__init__(self, "T8F81C2", _io, _connectors, toolchain=toolchain) def create_programmer(self): return OpenFPGALoader("fireant") diff --git a/litex_boards/platforms/kosagi_netv2.py b/litex_boards/platforms/kosagi_netv2.py index 9cab15a..48e61f0 100644 --- a/litex_boards/platforms/kosagi_netv2.py +++ b/litex_boards/platforms/kosagi_netv2.py @@ -191,12 +191,12 @@ class Platform(XilinxPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - def __init__(self, variant="a7-35"): + def __init__(self, variant="a7-35", toolchain="vivado"): device = { "a7-35": "xc7a35t-fgg484-2", "a7-100": "xc7a100t-fgg484-2" }[variant] - XilinxPlatform.__init__(self, device, _io, toolchain="vivado") + XilinxPlatform.__init__(self, device, _io, toolchain=toolchain) def create_programmer(self): bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit" diff --git a/litex_boards/platforms/krtkl_snickerdoodle.py b/litex_boards/platforms/krtkl_snickerdoodle.py index cf8793d..5b65d90 100644 --- a/litex_boards/platforms/krtkl_snickerdoodle.py +++ b/litex_boards/platforms/krtkl_snickerdoodle.py @@ -70,12 +70,12 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_freq = 100e6 - def __init__(self, variant="z7-10"): + def __init__(self, variant="z7-10", toolchain="vivado"): device = { "z7-10": "xc7z010-clg400-1", "z7-20": "xc7z020-clg400-3" }[variant] - XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado") + XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain) self.default_clk_period = 1e9 / self.default_clk_freq self.toolchain.bitstream_commands = [ "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]" diff --git a/litex_boards/platforms/lattice_ice40up5k_evn.py b/litex_boards/platforms/lattice_ice40up5k_evn.py index c00195a..3dc1681 100644 --- a/litex_boards/platforms/lattice_ice40up5k_evn.py +++ b/litex_boards/platforms/lattice_ice40up5k_evn.py @@ -116,9 +116,8 @@ class Platform(LatticePlatform): default_clk_name = "clk12" default_clk_period = 1e9/12e6 - def __init__(self): - LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, - toolchain="icestorm") + def __init__(self, toolchain="icestorm"): + LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain=toolchain) self.add_extension(serial) self.add_extension(spiflash) diff --git a/litex_boards/platforms/lattice_machxo3.py b/litex_boards/platforms/lattice_machxo3.py index 84034f2..7dd2824 100644 --- a/litex_boards/platforms/lattice_machxo3.py +++ b/litex_boards/platforms/lattice_machxo3.py @@ -44,8 +44,8 @@ class Platform(LatticePlatform): default_clk_name = "clk12" default_clk_period = 1e9/12e6 - def __init__(self): - LatticePlatform.__init__(self, "LCMXO3L-6900C-5BG256C", _io) + def __init__(self, toolchain="diamond"): + LatticePlatform.__init__(self, "LCMXO3L-6900C-5BG256C", _io, toolchain=toolchain) def create_programmer(self): _xcf_template = """ diff --git a/litex_boards/platforms/linsn_rv901t.py b/litex_boards/platforms/linsn_rv901t.py index a849cba..76f22db 100644 --- a/litex_boards/platforms/linsn_rv901t.py +++ b/litex_boards/platforms/linsn_rv901t.py @@ -291,8 +291,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk25" default_clk_period = 1e9/25e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc6slx16-2-ftg256", _io, _connectors) + def __init__(self, toolchain="ise"): + XilinxPlatform.__init__(self, "xc6slx16-2-ftg256", _io, _connectors, toolchain=toolchain) def create_programmer(self): return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc6slx16.bit") diff --git a/litex_boards/platforms/logicbone.py b/litex_boards/platforms/logicbone.py index d55c6b5..ed8849f 100644 --- a/litex_boards/platforms/logicbone.py +++ b/litex_boards/platforms/logicbone.py @@ -197,7 +197,7 @@ class Platform(LatticePlatform): self.revision = revision io = {"rev0": _io_rev0 }[revision] connectors = {"rev0": _connectors_rev0 }[revision] - LatticePlatform.__init__(self, f"LFE5UM5G-{device}-8BG381C", io, connectors, toolchain="trellis", **kwargs) + LatticePlatform.__init__(self, f"LFE5UM5G-{device}-8BG381C", io, connectors, toolchain=toolchain, **kwargs) def create_programmer(self): return DFUProg(vid="1d50", pid="6130") diff --git a/litex_boards/platforms/marble.py b/litex_boards/platforms/marble.py index f85e299..e09086c 100644 --- a/litex_boards/platforms/marble.py +++ b/litex_boards/platforms/marble.py @@ -320,8 +320,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk125" default_clk_period = 1e9 / 125e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7k160t-ffg676-2", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7k160t-ffg676-2", _io, _connectors, toolchain=toolchain) self.toolchain.bitstream_commands = [ "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]" ] diff --git a/litex_boards/platforms/marblemini.py b/litex_boards/platforms/marblemini.py index 33c493c..60a1b2c 100644 --- a/litex_boards/platforms/marblemini.py +++ b/litex_boards/platforms/marblemini.py @@ -250,8 +250,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk20_vcxo" default_clk_period = 1e9/20e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a100t-2fgg484", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7a100t-2fgg484", _io, _connectors, toolchain=toolchain) self.toolchain.bitstream_commands = [ "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]" ] diff --git a/litex_boards/platforms/micronova_mercury2.py b/litex_boards/platforms/micronova_mercury2.py index 91a05fa..2e3a552 100644 --- a/litex_boards/platforms/micronova_mercury2.py +++ b/litex_boards/platforms/micronova_mercury2.py @@ -54,8 +54,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a35tftg256-1", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7a35tftg256-1", _io, _connectors, toolchain=toolchain) def do_finalize(self,fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/mist.py b/litex_boards/platforms/mist.py index 312b1bf..5328a90 100644 --- a/litex_boards/platforms/mist.py +++ b/litex_boards/platforms/mist.py @@ -81,8 +81,8 @@ class Platform(AlteraPlatform): default_clk_name = "clk27" default_clk_period = 1e9/27e6 - def __init__(self): - AlteraPlatform.__init__(self, "EP3C25E144C8", _io) + def __init__(self, toolchain="quartus"): + AlteraPlatform.__init__(self, "EP3C25E144C8", _io, toolchain="quartus") self.add_platform_command("set_global_assignment -name FAMILY \"Cyclone III\"") self.add_platform_command("set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144") self.add_platform_command("set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED") diff --git a/litex_boards/platforms/mnt_rkx7.py b/litex_boards/platforms/mnt_rkx7.py index 2bf5202..5504e01 100644 --- a/litex_boards/platforms/mnt_rkx7.py +++ b/litex_boards/platforms/mnt_rkx7.py @@ -115,8 +115,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7k325t-ffg676-2", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7k325t-ffg676-2", _io, _connectors, toolchain=toolchain) def create_programmer(self): return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit") diff --git a/litex_boards/platforms/myminieye_runber.py b/litex_boards/platforms/myminieye_runber.py index 2764fe2..71fa640 100644 --- a/litex_boards/platforms/myminieye_runber.py +++ b/litex_boards/platforms/myminieye_runber.py @@ -103,8 +103,8 @@ class Platform(GowinPlatform): default_clk_name = "clk12" default_clk_period = 1e9/12e6 - def __init__(self): - GowinPlatform.__init__(self, "GW1N-UV4LQ144C6/I5", _io, _connectors, toolchain="gowin", devicename="GW1N-4") + def __init__(self, toolchain="gowin"): + GowinPlatform.__init__(self, "GW1N-UV4LQ144C6/I5", _io, _connectors, toolchain=toolchain, devicename="GW1N-4") self.toolchain.options["use_mspi_as_gpio"] = 1 def create_programmer(self): diff --git a/litex_boards/platforms/numato_aller.py b/litex_boards/platforms/numato_aller.py index e247084..41654c0 100644 --- a/litex_boards/platforms/numato_aller.py +++ b/litex_boards/platforms/numato_aller.py @@ -108,8 +108,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain=toolchain) self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") self.toolchain.bitstream_commands = [ "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", diff --git a/litex_boards/platforms/numato_mimas_a7.py b/litex_boards/platforms/numato_mimas_a7.py index 9c8d966..20b29b0 100644 --- a/litex_boards/platforms/numato_mimas_a7.py +++ b/litex_boards/platforms/numato_mimas_a7.py @@ -187,8 +187,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a50tfgg484-1", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7a50tfgg484-1", _io, _connectors, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = \ diff --git a/litex_boards/platforms/numato_tagus.py b/litex_boards/platforms/numato_tagus.py index ce6ad8a..a5f45ae 100644 --- a/litex_boards/platforms/numato_tagus.py +++ b/litex_boards/platforms/numato_tagus.py @@ -156,8 +156,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, _connectors, toolchain=toolchain) self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]") self.toolchain.bitstream_commands = [ diff --git a/litex_boards/platforms/pano_logic_g2.py b/litex_boards/platforms/pano_logic_g2.py index 3e46750..1c87fbe 100644 --- a/litex_boards/platforms/pano_logic_g2.py +++ b/litex_boards/platforms/pano_logic_g2.py @@ -132,10 +132,10 @@ class Platform(XilinxPlatform): default_clk_name = "clk125" default_clk_period = 1e9/125e6 - def __init__(self, revision="c"): + def __init__(self, revision="c", toolchain="ise"): assert revision in ["b", "c"] device = {"b": "xc6slx150-2-fgg484", "c": "xc6slx100-2-fgg484"}[revision] - XilinxPlatform.__init__(self, device, _io) + XilinxPlatform.__init__(self, device, _io, toolchain=toolchain) self.add_platform_command("""CONFIG VCCAUX="2.5";""") self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6) diff --git a/litex_boards/platforms/qmtech_10cl006.py b/litex_boards/platforms/qmtech_10cl006.py index 8df772e..c75d978 100644 --- a/litex_boards/platforms/qmtech_10cl006.py +++ b/litex_boards/platforms/qmtech_10cl006.py @@ -130,7 +130,7 @@ class Platform(AlteraPlatform): ), ] - def __init__(self, with_daughterboard=False): + def __init__(self, toolchain="quartus", with_daughterboard=False): device = "10CL006YU256C8G" io = _io connectors = _connectors @@ -143,7 +143,7 @@ class Platform(AlteraPlatform): else: io += self.core_resources - AlteraPlatform.__init__(self, device, io, connectors) + AlteraPlatform.__init__(self, device, io, connectors, toolchain=toolchain) if with_daughterboard: # an ethernet pin takes K22, so make it available diff --git a/litex_boards/platforms/qmtech_5cefa2.py b/litex_boards/platforms/qmtech_5cefa2.py index d886162..ec1749e 100644 --- a/litex_boards/platforms/qmtech_5cefa2.py +++ b/litex_boards/platforms/qmtech_5cefa2.py @@ -129,7 +129,7 @@ class Platform(AlteraPlatform): ), ] - def __init__(self, with_daughterboard=False): + def __init__(self, toolchain="quartus", with_daughterboard=False): device = "5CEFA2F23C8" io = _io connectors = _connectors @@ -142,7 +142,7 @@ class Platform(AlteraPlatform): else: io += self.core_resources - AlteraPlatform.__init__(self, device, io, connectors) + AlteraPlatform.__init__(self, device, io, connectors, toolchain=toolchain) if with_daughterboard: # ethernet takes the config pin, so make it available diff --git a/litex_boards/platforms/qmtech_ep4cex5.py b/litex_boards/platforms/qmtech_ep4cex5.py index d7292b5..4ad26f8 100644 --- a/litex_boards/platforms/qmtech_ep4cex5.py +++ b/litex_boards/platforms/qmtech_ep4cex5.py @@ -130,7 +130,7 @@ class Platform(AlteraPlatform): ), ] - def __init__(self, variant="ep4ce15", with_daughterboard=False): + def __init__(self, variant="ep4ce15", toolchain="quartus", with_daughterboard=False): device = { "ep4ce15": "EP4CE15F23C8", "ep4ce55": "EP4CE55F23C8" @@ -146,7 +146,7 @@ class Platform(AlteraPlatform): else: io += self.core_resources - AlteraPlatform.__init__(self, device, io, connectors) + AlteraPlatform.__init__(self, device, io, connectors, toolchain=toolchain) if with_daughterboard: # an ethernet pin takes K22, so make it available diff --git a/litex_boards/platforms/qmtech_wukong.py b/litex_boards/platforms/qmtech_wukong.py index 6f496c4..5df3e45 100644 --- a/litex_boards/platforms/qmtech_wukong.py +++ b/litex_boards/platforms/qmtech_wukong.py @@ -200,13 +200,13 @@ class Platform(XilinxPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - def __init__(self, board_version=1, speed_grade=-2): + def __init__(self, board_version=1, speed_grade=-2, toolchain="vivado"): io = _io_common if board_version < 2: io.extend(_io_v1) else: io.extend(_io_v2) - XilinxPlatform.__init__(self, "xc7a100t{}fgg676".format(speed_grade), io, _connectors, toolchain="vivado") + XilinxPlatform.__init__(self, "xc7a100t{}fgg676".format(speed_grade), io, _connectors, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = \ diff --git a/litex_boards/platforms/quicklogic_quickfeather.py b/litex_boards/platforms/quicklogic_quickfeather.py index 7d6e62f..d7f4eff 100644 --- a/litex_boards/platforms/quicklogic_quickfeather.py +++ b/litex_boards/platforms/quicklogic_quickfeather.py @@ -22,6 +22,6 @@ _io = [ # Platform ----------------------------------------------------------------------------------------- class Platform(QuickLogicPlatform): - def __init__(self): - QuickLogicPlatform.__init__(self, "ql-eos-s3", _io, toolchain="symbiflow") + def __init__(self, toolchain="symbiflow"): + QuickLogicPlatform.__init__(self, "ql-eos-s3", _io, toolchain=toolchain) diff --git a/litex_boards/platforms/redpitaya.py b/litex_boards/platforms/redpitaya.py index 63b7627..d3bb0fe 100644 --- a/litex_boards/platforms/redpitaya.py +++ b/litex_boards/platforms/redpitaya.py @@ -139,7 +139,7 @@ _connectors = [ class Platform(XilinxPlatform): - def __init__(self, board="redpitaya14"): + def __init__(self, board="redpitaya14", toolchain="vivado"): if board == "redpitaya14": device = "xc7z010clg400-1" extension = _io_14 @@ -153,7 +153,7 @@ class Platform(XilinxPlatform): self.default_clk_period = 1e9/self.default_clk_freq - XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado") + XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain) self.add_extension(extension) self.add_extension(_ps7_io) self.add_extension(_uart_io) diff --git a/litex_boards/platforms/rz_easyfpga.py b/litex_boards/platforms/rz_easyfpga.py index f67985d..e8a7e87 100644 --- a/litex_boards/platforms/rz_easyfpga.py +++ b/litex_boards/platforms/rz_easyfpga.py @@ -53,8 +53,8 @@ class Platform(AlteraPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - def __init__(self): - AlteraPlatform.__init__(self, "EP4CE6E22C8", _io) + def __init__(self, toolchain="quartus"): + AlteraPlatform.__init__(self, "EP4CE6E22C8", _io, toolchain=toolchain) def create_programmer(self): return USBBlaster() diff --git a/litex_boards/platforms/saanlima_pipistrello.py b/litex_boards/platforms/saanlima_pipistrello.py index 8c41665..1ac0426 100644 --- a/litex_boards/platforms/saanlima_pipistrello.py +++ b/litex_boards/platforms/saanlima_pipistrello.py @@ -157,8 +157,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors) + def __init__(self, toolchain="ise"): + XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors, toolchain="ise") self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6" def create_programmer(self): diff --git a/litex_boards/platforms/scarabhardware_minispartan6.py b/litex_boards/platforms/scarabhardware_minispartan6.py index 8d73fa9..37dd5ff 100644 --- a/litex_boards/platforms/scarabhardware_minispartan6.py +++ b/litex_boards/platforms/scarabhardware_minispartan6.py @@ -154,9 +154,9 @@ class Platform(XilinxPlatform): default_clk_name = "clk32" default_clk_period = 1e9/32e6 - def __init__(self, device="xc6slx25"): + def __init__(self, device="xc6slx25", toolchain="ise"): assert device in ["xc6slx9", "xc6slx25"] - XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors) + XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors, toolchain=toolchain) def create_programmer(self): return XC3SProg(cable="ftdi") diff --git a/litex_boards/platforms/seeedstudio_spartan_edge_accelerator.py b/litex_boards/platforms/seeedstudio_spartan_edge_accelerator.py index 73edb48..f3f1fea 100644 --- a/litex_boards/platforms/seeedstudio_spartan_edge_accelerator.py +++ b/litex_boards/platforms/seeedstudio_spartan_edge_accelerator.py @@ -110,8 +110,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7s15-ftgb196", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7s15-ftgb196", _io, _connectors, toolchain=toolchain) def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/siglent_sds1104xe.py b/litex_boards/platforms/siglent_sds1104xe.py index b0537df..7faa9af 100644 --- a/litex_boards/platforms/siglent_sds1104xe.py +++ b/litex_boards/platforms/siglent_sds1104xe.py @@ -112,8 +112,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk25" default_clk_period = 1e9/25e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io, _connectors, toolchain=toolchain) self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 33]") self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") diff --git a/litex_boards/platforms/sipeed_tang_nano.py b/litex_boards/platforms/sipeed_tang_nano.py index 364fe45..0977c37 100644 --- a/litex_boards/platforms/sipeed_tang_nano.py +++ b/litex_boards/platforms/sipeed_tang_nano.py @@ -47,9 +47,9 @@ class Platform(GowinPlatform): default_clk_name = "clk24" default_clk_period = 1e9/24e6 - def __init__(self): - GowinPlatform.__init__(self, "GW1N-LV1QN48C6/I5", _io, _connectors, toolchain="gowin", devicename="GW1N-1") - self.toolchain.options["use_done_as_gpio"] = 1 + def __init__(self, toolchain="gowin"): + GowinPlatform.__init__(self, "GW1N-LV1QN48C6/I5", _io, _connectors, toolchain=toolchain, devicename="GW1N-1") + self.toolchain.options["use_done_as_gpio"] = 1 self.toolchain.options["use_reconfign_as_gpio"] = 1 def create_programmer(self): diff --git a/litex_boards/platforms/sipeed_tang_nano_4k.py b/litex_boards/platforms/sipeed_tang_nano_4k.py index b804914..d705abf 100644 --- a/litex_boards/platforms/sipeed_tang_nano_4k.py +++ b/litex_boards/platforms/sipeed_tang_nano_4k.py @@ -86,8 +86,8 @@ class Platform(GowinPlatform): default_clk_name = "clk27" default_clk_period = 1e9/27e6 - def __init__(self): - GowinPlatform.__init__(self, "GW1NSR-LV4CQN48PC7/I6", _io, _connectors, toolchain="gowin", devicename="GW1NSR-4C") + def __init__(self, toolchain="gowin"): + GowinPlatform.__init__(self, "GW1NSR-LV4CQN48PC7/I6", _io, _connectors, toolchain=toolchain, devicename="GW1NSR-4C") self.toolchain.options["use_mode_as_gpio"] = 1 self.toolchain.options["use_mspi_as_gpio"] = 1 self.toolchain.options["use_done_as_gpio"] = 1 diff --git a/litex_boards/platforms/sipeed_tang_nano_9k.py b/litex_boards/platforms/sipeed_tang_nano_9k.py index 6758a0d..511cce3 100644 --- a/litex_boards/platforms/sipeed_tang_nano_9k.py +++ b/litex_boards/platforms/sipeed_tang_nano_9k.py @@ -74,8 +74,8 @@ class Platform(GowinPlatform): default_clk_name = "clk27" default_clk_period = 1e9/27e6 - def __init__(self): - GowinPlatform.__init__(self, "GW1NR-LV9QN88PC6/I5", _io, _connectors, toolchain="gowin", devicename="GW1NR-9C") + def __init__(self, toolchain="gowin"): + GowinPlatform.__init__(self, "GW1NR-LV9QN88PC6/I5", _io, _connectors, toolchain=toolchain, devicename="GW1NR-9C") self.toolchain.options["use_mspi_as_gpio"] = 1 def create_programmer(self): diff --git a/litex_boards/platforms/sipeed_tang_primer.py b/litex_boards/platforms/sipeed_tang_primer.py index b45de67..0d387dd 100644 --- a/litex_boards/platforms/sipeed_tang_primer.py +++ b/litex_boards/platforms/sipeed_tang_primer.py @@ -50,8 +50,8 @@ class Platform(AnlogicPlatform): default_clk_name = "clk24" default_clk_period = 1e9/24e6 - def __init__(self): - AnlogicPlatform.__init__(self, "EG4S20BG256", _io, _connectors, toolchain="td") + def __init__(self, toolchain="td"): + AnlogicPlatform.__init__(self, "EG4S20BG256", _io, _connectors, toolchain=toolchain) def create_programmer(self): return OpenFPGALoader("licheeTang") diff --git a/litex_boards/platforms/sqrl_acorn.py b/litex_boards/platforms/sqrl_acorn.py index 2113ec1..973c6e3 100644 --- a/litex_boards/platforms/sqrl_acorn.py +++ b/litex_boards/platforms/sqrl_acorn.py @@ -109,14 +109,14 @@ class Platform(XilinxPlatform): default_clk_name = "clk200" default_clk_period = 1e9/200e6 - def __init__(self, variant="cle-215+"): + def __init__(self, variant="cle-215+", toolchain="vivado"): device = { "cle-101": "xc7a100t-fgg484-2", "cle-215": "xc7a200t-fbg484-2", "cle-215+": "xc7a200t-fbg484-3" }[variant] - XilinxPlatform.__init__(self, device, _io, toolchain="vivado") + XilinxPlatform.__init__(self, device, _io, toolchain=toolchain) self.add_extension(_serial_io) self.add_extension(_sdcard_io) self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") diff --git a/litex_boards/platforms/sqrl_fk33.py b/litex_boards/platforms/sqrl_fk33.py index 01d3ce2..5b17b9a 100644 --- a/litex_boards/platforms/sqrl_fk33.py +++ b/litex_boards/platforms/sqrl_fk33.py @@ -82,8 +82,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk200" default_clk_period = 1e9/200e6 - def __init__(self): - XilinxPlatform.__init__(self, "xcvu33p-fsvh2104-2L-e-es1", _io, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xcvu33p-fsvh2104-2L-e-es1", _io, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() diff --git a/litex_boards/platforms/sqrl_xcu1525.py b/litex_boards/platforms/sqrl_xcu1525.py index 6f8b2a3..54b2752 100644 --- a/litex_boards/platforms/sqrl_xcu1525.py +++ b/litex_boards/platforms/sqrl_xcu1525.py @@ -269,8 +269,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk300" default_clk_period = 1e9/300e6 - def __init__(self): - XilinxPlatform.__init__(self, "xcvu9p-fsgd2104-2l-e", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xcvu9p-fsgd2104-2l-e", _io, _connectors, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() diff --git a/litex_boards/platforms/terasic_de0nano.py b/litex_boards/platforms/terasic_de0nano.py index 55087b1..3284ddc 100644 --- a/litex_boards/platforms/terasic_de0nano.py +++ b/litex_boards/platforms/terasic_de0nano.py @@ -132,8 +132,8 @@ class Platform(AlteraPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - def __init__(self): - AlteraPlatform.__init__(self, "EP4CE22F17C6", _io, _connectors) + def __init__(self, toolchain="quartus"): + AlteraPlatform.__init__(self, "EP4CE22F17C6", _io, _connectors, toolchain=toolchain) def create_programmer(self): return USBBlaster() diff --git a/litex_boards/platforms/terasic_de10lite.py b/litex_boards/platforms/terasic_de10lite.py index 628e691..e4bbe53 100644 --- a/litex_boards/platforms/terasic_de10lite.py +++ b/litex_boards/platforms/terasic_de10lite.py @@ -122,8 +122,8 @@ class Platform(AlteraPlatform): default_clk_period = 1e9/50e6 create_rbf = False - def __init__(self): - AlteraPlatform.__init__(self, "10M50DAF484C7G", _io) + def __init__(self, toolchain="quartus"): + AlteraPlatform.__init__(self, "10M50DAF484C7G", _io, toolchain=toolchain) self.add_platform_command("set_global_assignment -name FAMILY \"MAX 10\"") self.add_platform_command("set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF") self.add_platform_command("set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE \"SINGLE IMAGE WITH ERAM\"") diff --git a/litex_boards/platforms/terasic_de10nano.py b/litex_boards/platforms/terasic_de10nano.py index c7a1e7d..be436a0 100644 --- a/litex_boards/platforms/terasic_de10nano.py +++ b/litex_boards/platforms/terasic_de10nano.py @@ -166,8 +166,8 @@ class Platform(AlteraPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - def __init__(self): - AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io) + def __init__(self, toolchain="quartus"): + AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io, toolchain=toolchain) self.add_extension(_mister_sdram_module_io) def create_programmer(self): diff --git a/litex_boards/platforms/terasic_de1soc.py b/litex_boards/platforms/terasic_de1soc.py index 19bc987..c0cf4e1 100644 --- a/litex_boards/platforms/terasic_de1soc.py +++ b/litex_boards/platforms/terasic_de1soc.py @@ -130,8 +130,8 @@ class Platform(AlteraPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - def __init__(self): - AlteraPlatform.__init__(self, "5CSEMA5F31C6", _io, _connectors) + def __init__(self, toolchain="quartus"): + AlteraPlatform.__init__(self, "5CSEMA5F31C6", _io, _connectors, toolchain=toolchain) def create_programmer(self): return USBBlaster(cable_name="DE-SoC", device_id=2) diff --git a/litex_boards/platforms/terasic_de2_115.py b/litex_boards/platforms/terasic_de2_115.py index 8555ecf..bc93244 100644 --- a/litex_boards/platforms/terasic_de2_115.py +++ b/litex_boards/platforms/terasic_de2_115.py @@ -46,8 +46,8 @@ class Platform(AlteraPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - def __init__(self): - AlteraPlatform.__init__(self, "EP4CE115F29C7", _io) + def __init__(self, toolchain="quartus"): + AlteraPlatform.__init__(self, "EP4CE115F29C7", _io, toolchain=toolchain) def create_programmer(self): return USBBlaster() diff --git a/litex_boards/platforms/terasic_deca.py b/litex_boards/platforms/terasic_deca.py index 679f055..65f915f 100644 --- a/litex_boards/platforms/terasic_deca.py +++ b/litex_boards/platforms/terasic_deca.py @@ -292,8 +292,8 @@ class Platform(AlteraPlatform): default_clk_period = 1e9/50e6 create_rbf = False - def __init__(self): - AlteraPlatform.__init__(self, "10M50DAF484C6GES", _io, _connectors) + def __init__(self, toolchain="quartus"): + AlteraPlatform.__init__(self, "10M50DAF484C6GES", _io, _connectors, toolchain=toolchain) # Disable config pin so bank8 can use 1.2V. self.add_platform_command("set_global_assignment -name AUTO_RESTART_CONFIGURATION ON") self.add_platform_command("set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF") diff --git a/litex_boards/platforms/terasic_sockit.py b/litex_boards/platforms/terasic_sockit.py index 27ef2df..2153a88 100644 --- a/litex_boards/platforms/terasic_sockit.py +++ b/litex_boards/platforms/terasic_sockit.py @@ -186,10 +186,10 @@ class Platform(AlteraPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - def __init__(self, revision="revd"): + def __init__(self, revision="revd", toolchain="quartus"): assert revision in _device_map.keys() self.revision = revision - AlteraPlatform.__init__(self, _device_map[revision], _io, connectors=_connectors_hsmc_gpio_daughterboard) + AlteraPlatform.__init__(self, _device_map[revision], _io, connectors=_connectors_hsmc_gpio_daughterboard, toolchain=toolchain) def create_programmer(self): return USBBlaster(cable_name="CV SoCKit") diff --git a/litex_boards/platforms/trenz_c10lprefkit.py b/litex_boards/platforms/trenz_c10lprefkit.py index 01dabad..df198df 100644 --- a/litex_boards/platforms/trenz_c10lprefkit.py +++ b/litex_boards/platforms/trenz_c10lprefkit.py @@ -126,8 +126,8 @@ class Platform(AlteraPlatform): default_clk_name = "clk12" default_clk_period = 1e9/12e6 - def __init__(self): - AlteraPlatform.__init__(self, "10CL055YU484A7G", _io) + def __init__(self, toolchain="quartus"): + AlteraPlatform.__init__(self, "10CL055YU484A7G", _io, toolchain=toolchain) def create_programmer(self): return USBBlaster(cable_name="Arrow-USB-Blaster") diff --git a/litex_boards/platforms/trenz_cyc1000.py b/litex_boards/platforms/trenz_cyc1000.py index bb4af93..4ba7caf 100644 --- a/litex_boards/platforms/trenz_cyc1000.py +++ b/litex_boards/platforms/trenz_cyc1000.py @@ -67,8 +67,8 @@ class Platform(AlteraPlatform): default_clk_name = "clk12" default_clk_period = 1e9/12e6 - def __init__(self): - AlteraPlatform.__init__(self, "10CL025YU256C8G", _io) + def __init__(self, toolchain="quartus"): + AlteraPlatform.__init__(self, "10CL025YU256C8G", _io, toolchain=toolchain) def create_programmer(self): return USBBlaster(cable_name="Arrow-USB-Blaster") diff --git a/litex_boards/platforms/trenz_max1000.py b/litex_boards/platforms/trenz_max1000.py index 88280ba..9772cf7 100644 --- a/litex_boards/platforms/trenz_max1000.py +++ b/litex_boards/platforms/trenz_max1000.py @@ -86,8 +86,8 @@ class Platform(AlteraPlatform): default_clk_name = "clk12" default_clk_period = 1e9/12e6 - def __init__(self): - AlteraPlatform.__init__(self, "10M08SAU169C8G", _io) + def __init__(self, toolchain="quartus"): + AlteraPlatform.__init__(self, "10M08SAU169C8G", _io, toolchain=toolchain) self.add_platform_command("set_global_assignment -name FAMILY \"MAX 10\"") self.add_platform_command("set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF") self.add_platform_command("set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE \"SINGLE IMAGE WITH ERAM\"") diff --git a/litex_boards/platforms/trenz_te0725.py b/litex_boards/platforms/trenz_te0725.py index b6a755f..11903da 100644 --- a/litex_boards/platforms/trenz_te0725.py +++ b/litex_boards/platforms/trenz_te0725.py @@ -78,8 +78,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a35tcsg324-2", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7a35tcsg324-2", _io, _connectors, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = \ diff --git a/litex_boards/platforms/trenz_tec0117.py b/litex_boards/platforms/trenz_tec0117.py index 179e792..c109f20 100644 --- a/litex_boards/platforms/trenz_tec0117.py +++ b/litex_boards/platforms/trenz_tec0117.py @@ -108,8 +108,8 @@ class Platform(GowinPlatform): default_clk_name = "clk12" default_clk_period = 1e9/12e6 - def __init__(self): - GowinPlatform.__init__(self, "GW1NR-LV9QN88C6/I5", _io, _connectors, toolchain="gowin", devicename='GW1NR-9') + def __init__(self, toolchain="gowin"): + GowinPlatform.__init__(self, "GW1NR-LV9QN88C6/I5", _io, _connectors, toolchain=toolchain, devicename="GW1NR-9") def create_programmer(self): return OpenFPGALoader("littleBee") diff --git a/litex_boards/platforms/tul_pynq_z2.py b/litex_boards/platforms/tul_pynq_z2.py index 61b763f..d652540 100644 --- a/litex_boards/platforms/tul_pynq_z2.py +++ b/litex_boards/platforms/tul_pynq_z2.py @@ -87,8 +87,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk125" default_clk_period = 1e9/125e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7z020clg400-1", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7z020clg400-1", _io, _connectors, toolchain=toolchain) self.add_extension(_ps7_io) self.add_extension(_usb_uart_pmod_io) diff --git a/litex_boards/platforms/xilinx_ac701.py b/litex_boards/platforms/xilinx_ac701.py index 1417d9d..de2ea58 100644 --- a/litex_boards/platforms/xilinx_ac701.py +++ b/litex_boards/platforms/xilinx_ac701.py @@ -234,8 +234,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk156" default_clk_period = 1e9/156.5e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a200t-fbg676-2", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7a200t-fbg676-2", _io, _connectors, toolchain=toolchain) self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 33]") diff --git a/litex_boards/platforms/xilinx_alveo_u250.py b/litex_boards/platforms/xilinx_alveo_u250.py index 3cfe6a8..de73452 100644 --- a/litex_boards/platforms/xilinx_alveo_u250.py +++ b/litex_boards/platforms/xilinx_alveo_u250.py @@ -332,8 +332,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk300" default_clk_period = 1e9/300e6 - def __init__(self): - XilinxPlatform.__init__(self, "xcu250-figd2104-2L-e", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xcu250-figd2104-2L-e", _io, _connectors, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() diff --git a/litex_boards/platforms/xilinx_alveo_u280.py b/litex_boards/platforms/xilinx_alveo_u280.py index 764af5f..8abcd1a 100644 --- a/litex_boards/platforms/xilinx_alveo_u280.py +++ b/litex_boards/platforms/xilinx_alveo_u280.py @@ -224,8 +224,8 @@ class Platform(XilinxPlatform): default_clk_name = "sysclk" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xcu280-fsvh2892-2L-e-es1", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xcu280-fsvh2892-2L-e-es1", _io, _connectors, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() diff --git a/litex_boards/platforms/xilinx_kc705.py b/litex_boards/platforms/xilinx_kc705.py index 924a3b2..85f12ad 100644 --- a/litex_boards/platforms/xilinx_kc705.py +++ b/litex_boards/platforms/xilinx_kc705.py @@ -534,8 +534,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk156" default_clk_period = 1e9/156.5e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain=toolchain) self.add_platform_command(""" set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 2.5 [current_design] diff --git a/litex_boards/platforms/xilinx_kcu105.py b/litex_boards/platforms/xilinx_kcu105.py index 92c3f1a..68c5b54 100644 --- a/litex_boards/platforms/xilinx_kcu105.py +++ b/litex_boards/platforms/xilinx_kcu105.py @@ -522,8 +522,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk125" default_clk_period = 1e9/125e6 - def __init__(self): - XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() diff --git a/litex_boards/platforms/xilinx_kv260.py b/litex_boards/platforms/xilinx_kv260.py index 838259d..643fea6 100644 --- a/litex_boards/platforms/xilinx_kv260.py +++ b/litex_boards/platforms/xilinx_kv260.py @@ -25,8 +25,8 @@ class Platform(XilinxPlatform): default_clk_name = "pmod_hda16_cc" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xck26-sfvc784-2lv-c", _io, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xck26-sfvc784-2lv-c", _io, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", ] self.default_clk_freq = 1e9 / self.default_clk_period diff --git a/litex_boards/platforms/xilinx_sp605.py b/litex_boards/platforms/xilinx_sp605.py index c274832..bd1978f 100644 --- a/litex_boards/platforms/xilinx_sp605.py +++ b/litex_boards/platforms/xilinx_sp605.py @@ -171,8 +171,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk200" default_clk_period = 1e9/200e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors, toolchain="ise") + def __init__(self, toolchain="ise"): + XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors, toolchain=toolchain) def create_programmer(self): return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc6slx45.bit") diff --git a/litex_boards/platforms/xilinx_vc707.py b/litex_boards/platforms/xilinx_vc707.py index 19c91af..f3e4518 100644 --- a/litex_boards/platforms/xilinx_vc707.py +++ b/litex_boards/platforms/xilinx_vc707.py @@ -631,8 +631,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk156" default_clk_period = 1e9/156.25e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7vx485tffg1761-2", _io, _connectors, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7vx485tffg1761-2", _io, _connectors, toolchain=toolchain) self.add_platform_command("""set_property CFGBVS VCCO [current_design]""") self.add_platform_command("""set_property CONFIG_VOLTAGE 2.5 [current_design]""") diff --git a/litex_boards/platforms/xilinx_vcu118.py b/litex_boards/platforms/xilinx_vcu118.py index ab1b77d..0cc7c31 100644 --- a/litex_boards/platforms/xilinx_vcu118.py +++ b/litex_boards/platforms/xilinx_vcu118.py @@ -181,7 +181,7 @@ class Platform(XilinxPlatform): default_clk_name = "clk125" default_clk_period = 1e9/125e6 - def __init__(self): + def __init__(self, toolchain="vivado"): XilinxPlatform.__init__(self, "xcvu9p-flga2104-2-e", _io, _connectors, toolchain="vivado") def create_programmer(self): diff --git a/litex_boards/platforms/xilinx_zcu104.py b/litex_boards/platforms/xilinx_zcu104.py index 4e4b47f..4ace7b6 100644 --- a/litex_boards/platforms/xilinx_zcu104.py +++ b/litex_boards/platforms/xilinx_zcu104.py @@ -108,8 +108,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk125" default_clk_period = 1e9/125e6 - def __init__(self): - XilinxPlatform.__init__(self, "xczu7ev-ffvc1156-2-i", _io, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xczu7ev-ffvc1156-2-i", _io, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() diff --git a/litex_boards/platforms/xilinx_zcu106.py b/litex_boards/platforms/xilinx_zcu106.py index 25deb9f..f5348c7 100644 --- a/litex_boards/platforms/xilinx_zcu106.py +++ b/litex_boards/platforms/xilinx_zcu106.py @@ -95,8 +95,8 @@ class Platform(XilinxPlatform): default_clk_name = "clk125" default_clk_period = 1e9/125e6 - def __init__(self): - XilinxPlatform.__init__(self, "xczu7ev-ffvc1156-2-e", _io, toolchain="vivado") + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xczu7ev-ffvc1156-2-e", _io, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() diff --git a/litex_boards/platforms/ztex213.py b/litex_boards/platforms/ztex213.py index d4159b3..e3c67c7 100644 --- a/litex_boards/platforms/ztex213.py +++ b/litex_boards/platforms/ztex213.py @@ -140,7 +140,7 @@ class Platform(XilinxPlatform): default_clk_name = "clk48" default_clk_period = 1e9/48e6 - def __init__(self, variant="ztex2.13a", expansion="debug"): + def __init__(self, variant="ztex2.13a", toolchain="vivado", expansion="debug"): device = { "ztex2.13a": "xc7a35tcsg324-1", #"ztex2.13b": "xc7a50tcsg324-1", #untested @@ -148,7 +148,7 @@ class Platform(XilinxPlatform): #"ztex2.13c": "xc7a75tcsg324-2", #untested #"ztex2.13d": "xc7a100tcsg324-2", #untested }[variant] - XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado") + XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain) if (expansion == "debug"): self.add_extension(_debug_io) else: