diff --git a/litex_boards/platforms/terasic_sockit.py b/litex_boards/platforms/terasic_sockit.py index e71c961..27ef2df 100644 --- a/litex_boards/platforms/terasic_sockit.py +++ b/litex_boards/platforms/terasic_sockit.py @@ -12,16 +12,16 @@ from litex.build.generic_platform import Pins, IOStandard, Subsignal, Misc # IOs ---------------------------------------------------------------------------------------------- _io = [ - # Clk + # Clk. ("clk50", 0, Pins("AF14"), IOStandard("3.3-V LVTTL")), - # Leds + # Leds. ("user_led", 0, Pins("AF10"), IOStandard("3.3-V LVTTL")), ("user_led", 1, Pins("AD10"), IOStandard("3.3-V LVTTL")), ("user_led", 2, Pins("AE11"), IOStandard("3.3-V LVTTL")), ("user_led", 3, Pins("AD7"), IOStandard("3.3-V LVTTL")), - # Buttons + # Buttons. ("user_btn", 0, Pins("AE9"), IOStandard("3.3-V LVTTL")), ("user_btn", 1, Pins("AE12"), IOStandard("3.3-V LVTTL")), ("user_btn", 2, Pins("AD9"), IOStandard("3.3-V LVTTL")), @@ -33,7 +33,7 @@ _io = [ ("user_sw", 2, Pins("AC28"), IOStandard("3.3-V LVTTL")), ("user_sw", 3, Pins("AC29"), IOStandard("3.3-V LVTTL")), - # MiSTer SDRAM via GPIO expansion board J2 + # MiSTer SDRAM (via GPIO expansion board on J2). ("sdram_clock", 0, Pins("D10"), IOStandard("3.3-V LVTTL")), ("sdram", 0, Subsignal("a", Pins( @@ -41,8 +41,7 @@ _io = [ "D12 A11 B6 D11 A10")), Subsignal("ba", Pins("B5 A4")), Subsignal("cs_n", Pins("A3")), - # CKE not connected on XS 2.2/2.4 - Subsignal("cke", Pins("B3")), + Subsignal("cke", Pins("B3")), # CKE not connected on XS 2.2/2.4. Subsignal("ras_n", Pins("E9")), Subsignal("cas_n", Pins("A6")), Subsignal("we_n", Pins("A5")), @@ -50,13 +49,12 @@ _io = [ "F14 G15 F15 H15 G13 A13 H14 B13", "C13 C8 B12 B8 F13 C12 B11 E13"), ), - # DQML/DQMH not connected on XS 2.2/2.4 - Subsignal("dm", Pins("AB27 AA26")), + Subsignal("dm", Pins("AB27 AA26")), # DQML/DQMH not connected on XS 2.2/2.4 IOStandard("3.3-V LVTTL"), Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""), ), - # DDR3 SDRAM + # DDR3 SDRAM. ("ddram", 0, Subsignal("a", Pins( "AJ14 AK14 AH12 AJ12 AG15 AH15 AK12 AK13", @@ -108,7 +106,7 @@ _io = [ Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT") ), - # VGA + # VGA. ("vga", 0, Subsignal("sync_n", Pins("AG2")), Subsignal("blank_n", Pins("AH3")), @@ -121,13 +119,13 @@ _io = [ IOStandard("3.3-V LVTTL") ), - # IrDA + # IrDA. ("irda", 0, Subsignal("irda_rxd", Pins("AH2")), IOStandard("3.3-V LVTTL") ), - # Temperatue + # Temperatue. ("temperature", 0, Subsignal("temp_cs_n", Pins("AF8")), Subsignal("temp_din", Pins("AG7")), @@ -136,7 +134,7 @@ _io = [ IOStandard("3.3-V LVTTL") ), - # Audio + # Audio. ("audio", 0, Subsignal("aud_adclrck", Pins("AG30")), Subsignal("aud_adcdat", Pins("AC27")), @@ -150,6 +148,7 @@ _io = [ IOStandard("3.3-V LVTTL") ), + # GPIO Serial. ("gpio_serial", 0, Subsignal("tx", Pins("J3:9")), Subsignal("rx", Pins("J3:10")), @@ -157,24 +156,22 @@ _io = [ ] # Connectors --------------------------------------------------------------------------------------- -# Since the numbering of the connectors in the documentation is 1-based -# I added a dummy pin (-) to the beginning to each connector -# to make the numbering in the code consistent with the documentation + _connectors_hsmc_gpio_daughterboard = [ ("J2", "- G15 F14 H15 F15 A13 G13 B13 H14 B11 E13 - - " + "C12 F13 B8 B12 C8 C13 A10 D10 A11 D11 B7 D12 C7 E12 A5 D9 - - " + "A6 E9 A3 B5 A4 B6 B1 C2 B2 D2"), - ("J2p", "- D1 E1 E11 F11"), # top to bottom, starting with 57 + ("J2p", "- D1 E1 E11 F11"), # Top to bottom, starting with 57. ("J3", "- AB27 F8 AA26 F9 B3 G8 C3 H8 D4 H7 - - " + "E4 J7 E2 K8 E3 K7 E6 J9 E7 J10 C4 J12 D5 G10 C5 J12 - - " + "D6 K12 F6 G11 G7 G12 D7 A8 E8 A9"), - ("J3p", "- C9 C10 H12 H13"), # top to bottom, starting with 117 + ("J3p", "- C9 C10 H12 H13"), # Top to bottom, starting with 117. ("J4", "- - - AD3 AE1 AD4 AE2 - - AB3 AC1 - - " + "AB4 AC2 - - Y3 AA1 Y4 AA2 - - V3 W1 V4 W2 - - - -" + "T3 U1 T4 R1 - R2 P3 U2 P4 -"), - ("J4p", "- M3 M4 - H3 H4 J14 AD29 - N1 N2 - J1 J2") # top to bottom, starting with 169 + ("J4p", "- M3 M4 - H3 H4 J14 AD29 - N1 N2 - J1 J2") # Top to bottom, starting with 169. ] # Platform ----------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/terasic_sockit.py b/litex_boards/targets/terasic_sockit.py index c28b7dd..ef7bfd2 100755 --- a/litex_boards/targets/terasic_sockit.py +++ b/litex_boards/targets/terasic_sockit.py @@ -4,36 +4,29 @@ # # Copyright (c) 2020 Hans Baier # SPDX-License-Identifier: BSD-2-Clause -""" - This class provides basic support for the Arrow SoCKit. - Since the SoCKit has its USB2UART attached to the HPS - system, it is not available to the FPGA and thus the only - way to communicate is via JTAG serial which is configured - by default. - To access it, you can use the nios2_terminal application - included in the Intel/Altera quartus distribution. -""" import os import argparse -from migen.fhdl.module import Module -from migen.fhdl.structure import Signal, ClockDomain, ClockSignal - -from litex.soc.cores.clock import CycloneVPLL -from litex.soc.integration.builder import Builder, builder_args, builder_argdict -from litex.soc.integration.soc_core import SoCCore, soc_core_argdict, soc_core_args -from litex.soc.cores.led import LedChaser -from litex.soc.cores.video import VideoVGAPHY - -from litex.build.io import DDROutput - +from migen import * from litex_boards.platforms import terasic_sockit -from litedram.modules import _TechnologyTimings, _SpeedgradeTimings, SDRModule, AS4C32M16 -from litedram.phy import HalfRateGENSDRPHY, GENSDRPHY +from litex.soc.cores.clock import CycloneVPLL +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser +from litex.soc.cores.video import VideoVGAPHY + +from litex.build.io import DDROutput + +from litedram.modules import AS4C32M16 +from litedram.phy import HalfRateGENSDRPHY, GENSDRPHY # DRAM Module for XS board v2.2 ---------------------------------------------------------------------- +# FIXME: Move to litedram.modules. + +from litedram.modules import _TechnologyTimings, _SpeedgradeTimings, SDRModule + class W9825G6KH6(SDRModule): """ Winbond W9825G6KH-6 chip on Mister SDRAM XS board v2.2 @@ -77,8 +70,8 @@ class _CRG(Module): def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:2"): self.sdram_rate = sdram_rate self.rst = Signal() - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_vga = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_vga = ClockDomain(reset_less=True) if with_sdram: if sdram_rate == "1:2": self.clock_domains.cd_sys2x = ClockDomain() @@ -126,11 +119,7 @@ class BaseSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate) - # Leds ------------------------------------------------------------------------------------- - self.submodules.leds = LedChaser( - pads = platform.request_all("user_led"), - sys_clk_freq = sys_clk_freq) - + # SDR SDRAM -------------------------------------------------------------------------------- if mister_sdram == "xs_v22": sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) @@ -165,6 +154,11 @@ class BaseSoC(SoCCore): self.submodules.videophy = VideoVGAPHY(vga_pads, clock_domain="vga") self.add_video_terminal(phy=self.videophy, timings="1024x768@60Hz", clock_domain="vga") + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + # Build -------------------------------------------------------------------------------------------- def main():