diff --git a/litex_boards/platforms/digilent_cmod_a7.py b/litex_boards/platforms/digilent_cmod_a7.py
index 0818afb..c6bb8b4 100644
--- a/litex_boards/platforms/digilent_cmod_a7.py
+++ b/litex_boards/platforms/digilent_cmod_a7.py
@@ -69,6 +69,10 @@ class Platform(XilinxPlatform):
                 }[variant]
         XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
 
+    def create_programmer(self):
+        bscan_spi = "bscan_spi_xc7a15t.bit" if "xc7a15t" in self.device else "bscan_spi_xc7a35t.bit"
+        return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
+
     def do_finalize(self,fragment):
         XilinxPlatform.do_finalize(self, fragment)
         self.add_period_constraint(self.lookup_request("clk12", loose=True), self.default_clk_period)
diff --git a/litex_boards/targets/digilent_cmod_a7.py b/litex_boards/targets/digilent_cmod_a7.py
index aa1d2c0..92d9ae2 100755
--- a/litex_boards/targets/digilent_cmod_a7.py
+++ b/litex_boards/targets/digilent_cmod_a7.py
@@ -158,5 +158,9 @@ def main():
 
     builder.build(**builder_kwargs, run=args.build)
 
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
+
 if __name__ == "__main__":
     main()