From b9874685a513aa85facb04a970fcf263dbe296f7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 17 Jan 2023 15:43:12 +0100 Subject: [PATCH] gadgetfactory_papilio_pro: Cosmetic cleanups. --- .../platforms/gadgetfactory_papilio_pro.py | 81 +++++++++++++------ .../targets/gadgetfactory_papilio_pro.py | 34 ++++---- 2 files changed, 74 insertions(+), 41 deletions(-) diff --git a/litex_boards/platforms/gadgetfactory_papilio_pro.py b/litex_boards/platforms/gadgetfactory_papilio_pro.py index 41b8906..06d7b9e 100644 --- a/litex_boards/platforms/gadgetfactory_papilio_pro.py +++ b/litex_boards/platforms/gadgetfactory_papilio_pro.py @@ -1,48 +1,67 @@ +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2023 Fabien Caura +# SPDX-License-Identifier: BSD-2-Clause + from litex.build.generic_platform import * from litex.build.xilinx import XilinxSpartan6Platform from litex.build.xilinx.programmer import XC3SProg +# IOs ---------------------------------------------------------------------------------------------- _io = [ - ("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), - + # Clk / Rst. ("clk32", 0, Pins("P94"), IOStandard("LVCMOS33")), + # Leds. + ("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), + + # Serial. ("serial", 1, Subsignal("tx", Pins("P105"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), Subsignal("rx", Pins("P101"), IOStandard("LVCMOS33"), Misc("PULLUP")) ), + # SPIFlash ("spiflash", 0, Subsignal("cs_n", Pins("P38")), - Subsignal("clk", Pins("P70")), + Subsignal("clk", Pins("P70")), Subsignal("mosi", Pins("P64")), Subsignal("miso", Pins("P65"), Misc("PULLUP")), IOStandard("LVCMOS33"), Misc("SLEW=FAST") ), ("spiflash2x", 0, Subsignal("cs_n", Pins("P38")), - Subsignal("clk", Pins("P70")), - Subsignal("dq", Pins("P64", "P65")), + Subsignal("clk", Pins("P70")), + Subsignal("dq", Pins("P64", "P65")), IOStandard("LVCMOS33"), Misc("SLEW=FAST") ), + # SDR SDRAM. ("sdram_clock", 0, Pins("P32"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), ("sdram", 0, - Subsignal("a", Pins("P140 P139 P138 P137 P46 P45 P44", - "P43 P41 P40 P141 P35 P34")), - Subsignal("ba", Pins("P143 P142")), - Subsignal("cs_n", Pins("P1")), - Subsignal("cke", Pins("P33")), + Subsignal("a", Pins( + "P140 P139 P138 P137 P46 P45 P44", + "P43 P41 P40 P141 P35 P34" + )), + Subsignal("ba", Pins("P143 P142")), + Subsignal("cs_n", Pins("P1")), + Subsignal("cke", Pins("P33")), Subsignal("ras_n", Pins("P2")), Subsignal("cas_n", Pins("P5")), - Subsignal("we_n", Pins("P6")), - Subsignal("dq", Pins("P9 P10 P11 P12 P14 P15 P16 P8 P21 P22 P23 P24 P26 P27 P29 P30")), - Subsignal("dm", Pins("P7 P17")), + Subsignal("we_n", Pins("P6")), + Subsignal("dq", Pins( + "P9 P10 P11 P12 P14 P15 P16 P8", + "P21 P22 P23 P24 P26 P27 P29 P30" + )), + Subsignal("dm", Pins("P7 P17")), IOStandard("LVCMOS33"), Misc("SLEW=FAST") ) ] +# Connectors --------------------------------------------------------------------------------------- + _connectors = [ # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ("A", "P48 P51 P56 P58 P61 P66 P67 P75 P79 P81 P83 P85 P88 P93 P98 P100"), @@ -55,7 +74,7 @@ _connectors = [ # Arcade MegaWing V1.3 pinout _arcade_megawing = [ - # VGA + # VGA. ("vga", 0, Subsignal("r", Pins("C:4 C:5 C:6 C:7")), Subsignal("g", Pins("B:4 B:5 B:6 B:7")), @@ -64,19 +83,21 @@ _arcade_megawing = [ Subsignal("hsync_n", Pins("C:3")), IOStandard("LVCMOS33") ), - # Buttons + + # Buttons. ("buttons", 0, - Subsignal("up", Pins("C:8")), - Subsignal("down", Pins("C:10")), - Subsignal("left", Pins("C:11")), + Subsignal("up", Pins("C:8")), + Subsignal("down", Pins("C:10")), + Subsignal("left", Pins("C:11")), Subsignal("right", Pins("C:13")), IOStandard("LVCMOS33") ), - # Joysticks ports + + # Joysticks ports. ("joy", 0, - Subsignal("up", Pins("C:8")), - Subsignal("down", Pins("C:10")), - Subsignal("left", Pins("C:11")), + Subsignal("up", Pins("C:8")), + Subsignal("down", Pins("C:10")), + Subsignal("left", Pins("C:11")), Subsignal("right", Pins("C:13")), Subsignal("fire1", Pins("C:9")), Subsignal("fire2", Pins("C:15")), @@ -91,7 +112,8 @@ _arcade_megawing = [ Subsignal("fire2", Pins("A:3")), IOStandard("LVCMOS33") ), - # ps2 port + + # PS2 ports. ("ps2", 0, Subsignal("clk", Pins("C:1")), Subsignal("data", Pins("C:0")), @@ -102,22 +124,29 @@ _arcade_megawing = [ Subsignal("data", Pins("A:12")), IOStandard("LVCMOS33") ), - # LEDs + + # Leds. ("amw_user_led", 0, Pins("A:7"), IOStandard("LVCMOS33")), ("amw_user_led", 1, Pins("A:6"), IOStandard("LVCMOS33")), ("amw_user_led", 2, Pins("A:5"), IOStandard("LVCMOS33")), ("amw_user_led", 3, Pins("A:4"), IOStandard("LVCMOS33")), - # Reset button + # Reset button. ("reset_button", 0, Pins("P85"), IOStandard("LVCMOS33") ) ] +# Platform ----------------------------------------------------------------------------------------- + class Platform(XilinxSpartan6Platform): default_clk_name = "clk32" - default_clk_period = 31.25 + default_clk_period = 1e9/32e6 def __init__(self, toolchain="ise"): XilinxSpartan6Platform.__init__(self, "xc6slx9-tqg144-2", _io, _connectors, toolchain=toolchain) def create_programmer(self): return XC3SProg("papilio", "bscan_spi_lx9_papilio.bit") + + def do_finalize(self, fragment): + XilinxSpartan6Platform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk32", loose=True), 1e9/32e6) diff --git a/litex_boards/targets/gadgetfactory_papilio_pro.py b/litex_boards/targets/gadgetfactory_papilio_pro.py index c2dfbc0..00d88e7 100755 --- a/litex_boards/targets/gadgetfactory_papilio_pro.py +++ b/litex_boards/targets/gadgetfactory_papilio_pro.py @@ -25,16 +25,18 @@ from litex.soc.cores.led import LedChaser from litedram.modules import MT48LC4M16 from litedram.phy import s6ddrphy, GENSDRPHY, HalfRateGENSDRPHY +# CRG ---------------------------------------------------------------------------------------------- + class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"): - self.rst = Signal() - self.cd_sys = ClockDomain() + self.rst = Signal() + self.cd_sys = ClockDomain() if sdram_rate == "1:2": - self.cd_sys2x = ClockDomain() - self.cd_sys2x_ps = ClockDomain() + self.cd_sys2x = ClockDomain() + self.cd_sys2x_ps = ClockDomain() else: - self.cd_sys_ps = ClockDomain() - self.cd_vga = ClockDomain() + self.cd_sys_ps = ClockDomain() + self.cd_vga = ClockDomain() # # # @@ -58,11 +60,11 @@ class _CRG(LiteXModule): sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk) -### BaseSoC +# BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=80e6, - with_led_chaser=True, + with_led_chaser = True, with_video_terminal = False, **kwargs): platform = gadgetfactory_papilio_pro.Platform() @@ -85,31 +87,33 @@ class BaseSoC(SoCCore): l2_cache_size = 0 ) - # LEDs ------------------------------------------------------------------------------------- + # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - # Video Terminal + # Video Terminal --------------------------------------------------------------------------- if with_video_terminal: self.platform.add_extension(gadgetfactory_papilio_pro._arcade_megawing) self.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") +# Build -------------------------------------------------------------------------------------------- + def main(): from litex.build.parser import LiteXArgumentParser - parser = LiteXArgumentParser(platform=gadgetfactory_papilio_pro.Platform(), - description="LiteX SoC on Papilio Pro") - parser.add_argument("--sys-clk-freq", default=80e6, type=float, help="System clock frequency.") - parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).") + parser = LiteXArgumentParser(platform=gadgetfactory_papilio_pro.Platform, description="LiteX SoC on Papilio Pro.") + parser.add_target_argument("--sys-clk-freq", default=80e6, type=float, help="System clock frequency.") + parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).") args = parser.parse_args() soc = BaseSoC( - sys_clk_freq = args.sys_clk_freq, + sys_clk_freq = args.sys_clk_freq, with_video_terminal = args.with_video_terminal, **parser.soc_argdict ) + builder = Builder(soc, **parser.builder_argdict) if args.build: builder.build(**parser.toolchain_argdict)