diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index 3f3a4c5..e0eadd3 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -51,6 +51,7 @@ class _CRG(Module): # pll self.submodules.pll = pll = ECP5PLL() + self.comb += pll.reset.eq(~por_done) pll.register_clkin(clk27, 27e6) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) pll.create_clkout(self.cd_init, 27e6) @@ -65,8 +66,7 @@ class _CRG(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.cd_sys2x.rst, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked), - AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked) + AsyncResetSynchronizer(self.cd_sys, ~pll.locked) ] # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py index 662bd03..2f423f3 100755 --- a/litex_boards/targets/colorlight_5a_75x.py +++ b/litex_boards/targets/colorlight_5a_75x.py @@ -81,7 +81,7 @@ class _CRG(Module): # PLL self.submodules.pll = pll = ECP5PLL() - + self.comb += pll.reset.eq(~rst_n) pll.register_clkin(clk25, 25e6) pll.create_clkout(self.cd_sys, sys_clk_freq) if sdram_rate == "1:2": @@ -89,11 +89,11 @@ class _CRG(Module): pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased. else: pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) # Idealy 90° but needs to be increased. - self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | ~rst_n) # USB PLL if with_usb_pll: self.submodules.usb_pll = usb_pll = ECP5PLL() + self.comb += usb_pll.reset.eq(~rst_n) usb_pll.register_clkin(clk25, 25e6) self.clock_domains.cd_usb_12 = ClockDomain() self.clock_domains.cd_usb_48 = ClockDomain() diff --git a/litex_boards/targets/ecp5_evn.py b/litex_boards/targets/ecp5_evn.py index 95d5569..49688e0 100755 --- a/litex_boards/targets/ecp5_evn.py +++ b/litex_boards/targets/ecp5_evn.py @@ -40,7 +40,6 @@ class _CRG(Module): self.comb += pll.reset.eq(~rst_n) pll.register_clkin(clk, x5_clk_freq or 12e6) pll.create_clkout(self.cd_sys, sys_clk_freq) - self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/ecpix5.py b/litex_boards/targets/ecpix5.py index 8beaf9b..cfe72b6 100755 --- a/litex_boards/targets/ecpix5.py +++ b/litex_boards/targets/ecpix5.py @@ -54,6 +54,7 @@ class _CRG(Module): # PLL self.submodules.pll = pll = ECP5PLL() + self.comb += pll.reset.eq(~por_done | ~rst_n) pll.register_clkin(clk100, 100e6) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) pll.create_clkout(self.cd_init, 25e6) @@ -68,9 +69,8 @@ class _CRG(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n), - AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n | self.reset), - AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | ~rst_n | self.reset), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset), ] # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/hadbadge.py b/litex_boards/targets/hadbadge.py index bde9e7d..9a6e8fe 100755 --- a/litex_boards/targets/hadbadge.py +++ b/litex_boards/targets/hadbadge.py @@ -48,7 +48,6 @@ class _CRG(Module): pll.register_clkin(clk8, 8e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) - self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked) # SDRAM clock self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py index 586254d..d791eb5 100755 --- a/litex_boards/targets/logicbone.py +++ b/litex_boards/targets/logicbone.py @@ -39,7 +39,7 @@ class _CRG(Module): # # # - self.stop = Signal() + self.stop = Signal() self.reset = Signal() # Clk / Rst @@ -55,6 +55,7 @@ class _CRG(Module): # PLL sys2x_clk_ecsout = Signal() self.submodules.pll = pll = ECP5PLL() + self.comb += pll.reset.eq(~por_done) pll.register_clkin(clk25, 25e6) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) pll.create_clkout(self.cd_init, 24e6) @@ -73,9 +74,8 @@ class _CRG(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked), - AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | self.reset), - AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset), ] # USB PLL @@ -84,6 +84,7 @@ class _CRG(Module): self.clock_domains.cd_usb_48 = ClockDomain() usb_pll = ECP5PLL() self.submodules += usb_pll + self.comb += usb_pll.reset.eq(~por_done) usb_pll.register_clkin(clk25, 25e6) usb_pll.create_clkout(self.cd_usb_48, 48e6) usb_pll.create_clkout(self.cd_usb_12, 12e6) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 0f83d30..58b5de3 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -48,9 +48,9 @@ class _CRG(Module): # PLL self.submodules.pll = pll = ECP5PLL() + self.comb += pll.reset.eq(~por_done | ~rst_n) pll.register_clkin(clk48, 48e6) pll.create_clkout(self.cd_sys, sys_clk_freq) - self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n) # USB PLL if with_usb_pll: @@ -58,6 +58,7 @@ class _CRG(Module): self.clock_domains.cd_usb_48 = ClockDomain() usb_pll = ECP5PLL() self.submodules += usb_pll + self.comb += usb_pll.reset.eq(~por_done | ~rst_n) usb_pll.register_clkin(clk48, 48e6) usb_pll.create_clkout(self.cd_usb_48, 48e6) usb_pll.create_clkout(self.cd_usb_12, 12e6) @@ -92,6 +93,7 @@ class _CRGSDRAM(Module): # PLL sys2x_clk_ecsout = Signal() self.submodules.pll = pll = ECP5PLL() + self.comb += pll.reset.eq(~por_done | ~rst_n) pll.register_clkin(clk48, 48e6) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) pll.create_clkout(self.cd_init, 24e6) @@ -110,9 +112,8 @@ class _CRGSDRAM(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n), - AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n | self.reset), - AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | ~rst_n | self.reset), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset), ] # USB PLL @@ -121,6 +122,7 @@ class _CRGSDRAM(Module): self.clock_domains.cd_usb_48 = ClockDomain() usb_pll = ECP5PLL() self.submodules += usb_pll + self.comb += usb_pll.reset.eq(~por_done | ~rst_n) usb_pll.register_clkin(clk48, 48e6) usb_pll.create_clkout(self.cd_usb_48, 48e6) usb_pll.create_clkout(self.cd_usb_12, 12e6) diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index 93441c2..d29cd0e 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -49,9 +49,9 @@ class _CRG(Module): # PLL self.submodules.pll = pll = ECP5PLL() + self.comb += pll.reset.eq(~por_done | rst) pll.register_clkin(clk12, 12e6) pll.create_clkout(self.cd_sys, sys_clk_freq) - self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | rst) class _CRGSDRAM(Module): def __init__(self, platform, sys_clk_freq): @@ -80,6 +80,7 @@ class _CRGSDRAM(Module): # PLL sys2x_clk_ecsout = Signal() self.submodules.pll = pll = ECP5PLL() + self.comb += pll.reset.eq(~por_done | rst) pll.register_clkin(clk12, 12e6) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) pll.create_clkout(self.cd_init, 25e6) @@ -99,9 +100,8 @@ class _CRGSDRAM(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | rst), - AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | rst | self.reset), - AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | rst | self.reset), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset), ] self.comb += platform.request("dram_vtt_en").eq(1) diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py index d9baa60..ad6de73 100755 --- a/litex_boards/targets/ulx3s.py +++ b/litex_boards/targets/ulx3s.py @@ -58,11 +58,11 @@ class _CRG(Module): pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased. else: pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) - self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) # USB PLL if with_usb_pll: self.submodules.usb_pll = usb_pll = ECP5PLL() + self.comb += usb_pll.reset.eq(rst) usb_pll.register_clkin(clk25, 25e6) self.clock_domains.cd_usb_12 = ClockDomain() self.clock_domains.cd_usb_48 = ClockDomain() diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index 8b257b2..11d4d1a 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -56,6 +56,7 @@ class _CRG(Module): # PLL self.submodules.pll = pll = ECP5PLL() + self.comb += pll.reset.eq(~por_done | ~rst_n) pll.register_clkin(clk100, 100e6) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) pll.create_clkout(self.cd_init, 25e6) @@ -70,9 +71,8 @@ class _CRG(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n), - AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n | self.reset), - AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | ~rst_n | self.reset), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset), ] # BaseSoC ------------------------------------------------------------------------------------------