diff --git a/litex_boards/platforms/alveo_u250.py b/litex_boards/platforms/alveo_u250.py index f2ff5f8..2eb9d64 100644 --- a/litex_boards/platforms/alveo_u250.py +++ b/litex_boards/platforms/alveo_u250.py @@ -1,37 +1,68 @@ # This file is Copyright (c) 2020 David Shah +# This file is Copyright (c) 2020 Florent Kermarrec # License: BSD -# Note that this board file should also be applicable to -# the Alveo U200, VCU1525, BCU1525 and other 1525 variants. +# Note: This platform should also be applicable to the Alveo U200, VCU1525, BCU1525 and other +# 1525 variants. from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc from litex.build.xilinx import XilinxPlatform, VivadoProgrammer -# This part auto-generated by extract_xdc_pins.py +# IOs (initially auto-generated by extract_xdc_pins.py) --------------------------------------------- _io = [ - ("clk300", 0, + # clk / rst + ("clk300", 0, Subsignal("n", Pins("AY38"), IOStandard("DIFF_SSTL12")), Subsignal("p", Pins("AY37"), IOStandard("DIFF_SSTL12")), ), - ("clk300", 1, + ("clk300", 1, Subsignal("n", Pins("AW19"), IOStandard("DIFF_SSTL12")), Subsignal("p", Pins("AW20"), IOStandard("DIFF_SSTL12")), ), - ("clk300", 2, + ("clk300", 2, Subsignal("n", Pins("E32"), IOStandard("DIFF_SSTL12")), Subsignal("p", Pins("F32"), IOStandard("DIFF_SSTL12")), ), - ("clk300", 3, + ("clk300", 3, Subsignal("n", Pins("H16"), IOStandard("DIFF_SSTL12")), Subsignal("p", Pins("J16"), IOStandard("DIFF_SSTL12")), ), ("cpu_reset", 0, Pins("AL20"), IOStandard("LVCMOS12")), - ("ddr4_reset_gate", 0, Pins("AU21"), IOStandard("LVCMOS12")), - ("ddram", 0, + + # led + ("user_led", 0, Pins("BC21"), IOStandard("LVCMOS12")), + ("user_led", 1, Pins("BB21"), IOStandard("LVCMOS12")), + ("user_led", 2, Pins("BA20"), IOStandard("LVCMOS12")), + + # switches + ("set_sw", 0, Pins("AL21")), + ("user_sw", 0, Pins("AN22"), IOStandard("LVCMOS12")), + ("user_sw", 1, Pins("AM19"), IOStandard("LVCMOS12")), + ("user_sw", 2, Pins("AL19"), IOStandard("LVCMOS12")), + ("user_sw", 3, Pins("AP20"), IOStandard("LVCMOS12")), + + # gpio + ("gpio_msp", 0, Pins("AR20"), IOStandard("LVCMOS12")), + ("gpio_msp", 1, Pins("AM20"), IOStandard("LVCMOS12")), + ("gpio_msp", 2, Pins("AM21"), IOStandard("LVCMOS12")), + ("gpio_msp", 3, Pins("AN21"), IOStandard("LVCMOS12")), + + ("serial", 0, + Subsignal("rx", Pins("BF18"), IOStandard("LVCMOS12")), + Subsignal("tx", Pins("BB20"), IOStandard("LVCMOS12")), + ), + ("serial_msp", 0, + Subsignal("rx", Pins("BA19"), IOStandard("LVCMOS12")), + Subsignal("tx", Pins("BB19"), IOStandard("LVCMOS12")), + ), + + # ddram + ("ddram_reset_gate", 0, Pins("AU21"), IOStandard("LVCMOS12")), + ("ddram", 0, Subsignal("a", Pins( "AT36 AV36 AV37 AW35 AW36 AY36 AY35 BA40", - "BA37 BB37 AR35 BA39 BB40 AN36"), + "BA37 BB37 AR35 BA39 BB40 AN36"), IOStandard("SSTL12_DCI")), Subsignal("act_n", Pins("BB39"), IOStandard("SSTL12_DCI")), Subsignal("ba", Pins("AT35 AT34"), IOStandard("SSTL12_DCI")), @@ -49,21 +80,21 @@ _io = [ "AL30 AM30 AU32 AT32 AN31 AN32 AR32 AR31", "AP29 AP28 AN27 AM27 AN29 AM29 AR27 AR28", "AT28 AV27 AU27 AT27 AV29 AY30 AW30 AV28", - "BD34 BD33 BE33 BD35 BF32 BF33 BF34 BF35"), - IOStandard("POD12_DCI"), - Misc("PRE_EMPHASIS=RDRV_240"), + "BD34 BD33 BE33 BD35 BF32 BF33 BF34 BF35"), + IOStandard("POD12_DCI"), + Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), Subsignal("dqs_n", Pins( "BB30 BC26 BD29 BE26 BB36 BD31 AW33 BA33", - "AM32 AP31 AL29 AT30 AU30 AY28 BE36 BE32"), - IOStandard("DIFF_POD12"), - Misc("PRE_EMPHASIS=RDRV_240"), + "AM32 AP31 AL29 AT30 AU30 AY28 BE36 BE32"), + IOStandard("DIFF_POD12"), + Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), Subsignal("dqs_p", Pins( "BA30 BB26 BD28 BD26 BB35 BC31 AV33 BA32", - "AM31 AP30 AL28 AR30 AU29 AY27 BE35 BE31"), - IOStandard("DIFF_POD12"), - Misc("PRE_EMPHASIS=RDRV_240"), + "AM31 AP30 AL28 AR30 AU29 AY27 BE35 BE31"), + IOStandard("DIFF_POD12"), + Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), Subsignal("odt", Pins("AP34"), IOStandard("SSTL12_DCI")), Subsignal("ras_n", Pins("AR36"), IOStandard("SSTL12_DCI")), @@ -71,10 +102,10 @@ _io = [ Subsignal("we_n", Pins("AP35"), IOStandard("SSTL12_DCI")), Misc("SLEW=FAST") ), - ("ddram_ch2", 0, + ("ddram", 1, Subsignal("a", Pins( "AN24 AT24 AW24 AN26 AY22 AY23 AV24 BA22", - "AY25 BA23 AM26 BA25 BB22 AL24"), + "AY25 BA23 AM26 BA25 BB22 AL24"), IOStandard("SSTL12_DCI")), Subsignal("act_n", Pins("AW25"), IOStandard("SSTL12_DCI")), Subsignal("ba", Pins("AU24 AP26"), IOStandard("SSTL12_DCI")), @@ -92,21 +123,21 @@ _io = [ "BE13 BD14 BF12 BD13 BD15 BD16 BF14 BF13", "AY17 BA17 AY18 BA18 BA15 BB15 BC11 BD11", "AV16 AV17 AU16 AU17 BB17 BB16 AT18 AT17", - "AM15 AL15 AN17 AN16 AR18 AP18 AL17 AL16"), - IOStandard("POD12_DCI"), - Misc("PRE_EMPHASIS=RDRV_240"), + "AM15 AL15 AN17 AN16 AR18 AP18 AL17 AL16"), + IOStandard("POD12_DCI"), + Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), Subsignal("dqs_n", Pins( "BF9 BF8 AY15 AY12 BB10 BA9 AT13 AP14", - "BE11 BF15 BC12 BC14 AW18 AY16 AR16 AM16"), - IOStandard("DIFF_POD12"), - Misc("PRE_EMPHASIS=RDRV_240"), + "BE11 BF15 BC12 BC14 AW18 AY16 AR16 AM16"), + IOStandard("DIFF_POD12"), + Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), Subsignal("dqs_p", Pins( "BF10 BE8 AW15 AY13 BB11 BA10 AT14 AN14", - "BE12 BE15 BC13 BB14 AV18 AW16 AP16 AM17"), - IOStandard("DIFF_POD12"), - Misc("PRE_EMPHASIS=RDRV_240"), + "BE12 BE15 BC13 BB14 AV18 AW16 AP16 AM17"), + IOStandard("DIFF_POD12"), + Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), Subsignal("odt", Pins("AW23"), IOStandard("SSTL12_DCI")), Subsignal("ras_n", Pins("AN23"), IOStandard("SSTL12_DCI")), @@ -114,10 +145,10 @@ _io = [ Subsignal("we_n", Pins("AL25"), IOStandard("SSTL12_DCI")), Misc("SLEW=FAST") ), - ("ddram_ch3", 0, + ("ddram", 2, Subsignal("a", Pins( "L29 A33 C33 J29 H31 G31 C32 B32", - "A32 D31 A34 E31 M30 F33"), + "A32 D31 A34 E31 M30 F33"), IOStandard("SSTL12_DCI")), Subsignal("act_n", Pins("B31"), IOStandard("SSTL12_DCI")), Subsignal("ba", Pins("D33 B36"), IOStandard("SSTL12_DCI")), @@ -135,21 +166,21 @@ _io = [ "F35 E38 D38 E35 E36 E37 F38 G38", "P30 R30 P29 N29 L32 M32 P31 N32", "J35 K35 L33 K33 J34 J33 N34 P34", - "H36 G36 H37 J36 K37 K38 G35 G34"), - IOStandard("POD12_DCI"), - Misc("PRE_EMPHASIS=RDRV_240"), + "H36 G36 H37 J36 K37 K38 G35 G34"), + IOStandard("POD12_DCI"), + Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), Subsignal("dqs_n", Pins( "M26 P28 J26 L28 D30 H27 A28 B29", - "E40 F37 M31 R31 L36 L34 H38 H34"), - IOStandard("DIFF_POD12"), - Misc("PRE_EMPHASIS=RDRV_240"), + "E40 F37 M31 R31 L36 L34 H38 H34"), + IOStandard("DIFF_POD12"), + Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), Subsignal("dqs_p", Pins( "N26 R28 J25 M27 D29 H26 A27 C29", - "E39 G37 N31 T30 L35 M34 J38 H33"), - IOStandard("DIFF_POD12"), - Misc("PRE_EMPHASIS=RDRV_240"), + "E39 G37 N31 T30 L35 M34 J38 H33"), + IOStandard("DIFF_POD12"), + Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), Subsignal("odt", Pins("E33"), IOStandard("SSTL12_DCI")), Subsignal("ras_n", Pins("K30"), IOStandard("SSTL12_DCI")), @@ -157,10 +188,10 @@ _io = [ Subsignal("we_n", Pins("A35"), IOStandard("SSTL12_DCI")), Misc("SLEW=FAST") ), - ("ddram_ch4", 0, + ("ddram", 4, Subsignal("a", Pins( "K15 B15 F14 A15 C14 A14 B14 E13", - "F13 A13 D14 C13 B13 K16"), + "F13 A13 D14 C13 B13 K16"), IOStandard("SSTL12_DCI")), Subsignal("act_n", Pins("H13"), IOStandard("SSTL12_DCI")), Subsignal("ba", Pins("J15 H14"), IOStandard("SSTL12_DCI")), @@ -178,21 +209,21 @@ _io = [ "A23 A22 B24 B25 B22 C22 C24 C23", "C19 C18 C21 B21 A18 A17 A20 B20", "E17 F20 E18 E20 D19 D20 H18 J18", - "F22 E22 G22 G21 F24 E25 F25 G25"), - IOStandard("POD12_DCI"), - Misc("PRE_EMPHASIS=RDRV_240"), + "F22 E22 G22 G21 F24 E25 F25 G25"), + IOStandard("POD12_DCI"), + Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), Subsignal("dqs_n", Pins( "R22 N21 H21 L22 K20 K17 P18 M17", - "A24 D23 B17 A19 F17 G19 E23 H22"), - IOStandard("DIFF_POD12"), - Misc("PRE_EMPHASIS=RDRV_240"), + "A24 D23 B17 A19 F17 G19 E23 H22"), + IOStandard("DIFF_POD12"), + Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), Subsignal("dqs_p", Pins( "T22 N22 J21 M22 L20 K18 P19 N17", - "A25 D24 C17 B19 F18 H19 F23 H23"), - IOStandard("DIFF_POD12"), - Misc("PRE_EMPHASIS=RDRV_240"), + "A25 D24 C17 B19 F18 H19 F23 H23"), + IOStandard("DIFF_POD12"), + Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), Subsignal("odt", Pins("C16"), IOStandard("SSTL12_DCI")), Subsignal("ras_n", Pins("F15"), IOStandard("SSTL12_DCI")), @@ -200,31 +231,33 @@ _io = [ Subsignal("we_n", Pins("D15"), IOStandard("SSTL12_DCI")), Misc("SLEW=FAST") ), - ("dip_sw", 0, Pins("AN22"), IOStandard("LVCMOS12")), - ("dip_sw", 1, Pins("AM19"), IOStandard("LVCMOS12")), - ("dip_sw", 2, Pins("AL19"), IOStandard("LVCMOS12")), - ("dip_sw", 3, Pins("AP20"), IOStandard("LVCMOS12")), - ("gpio_msp", 0, Pins("AR20"), IOStandard("LVCMOS12")), - ("gpio_msp", 1, Pins("AM20"), IOStandard("LVCMOS12")), - ("gpio_msp", 2, Pins("AM21"), IOStandard("LVCMOS12")), - ("gpio_msp", 3, Pins("AN21"), IOStandard("LVCMOS12")), - ("i2c", 0, + + # i2c + ("i2c_rst_n", 0, Pins("BF19"), IOStandard("LVCMOS12")), + ("i2c", 0, Subsignal("scl", Pins("BF20"), IOStandard("LVCMOS12")), Subsignal("sda", Pins("BF17"), IOStandard("LVCMOS12")), ), - ("i2c_main_reset_n", 0, Pins("BF19"), IOStandard("LVCMOS12")), - ("mgt_si570_clock", 0, + + # si570 + ("user_si570_clock", 0, + Subsignal("n", Pins("AV19"), IOStandard("DIFF_SSTL12")), + Subsignal("p", Pins("AU19"), IOStandard("DIFF_SSTL12")), + ), + ("mgt_si570_clock", 0, Subsignal("n", Pins("M10")), Subsignal("p", Pins("M11")), ), - ("mgt_si570_clock", 1, + ("mgt_si570_clock", 1, Subsignal("n", Pins("T10")), Subsignal("p", Pins("T11")), ), - ("pcie_x16", 0, + + # pcie + ("pcie_x16", 0, + Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), Subsignal("clk_n", Pins("AM10")), Subsignal("clk_p", Pins("AM11")), - Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), Subsignal("rx_n", Pins( "AF1 AG3 AH1 AJ3 AK1 AL3 AM1 AN3", "AP1 AR3 AT1 AU3 AV1 AW3 BA1 BC1")), @@ -238,7 +271,9 @@ _io = [ "AF7 AG9 AH7 AJ9 AK7 AL9 AM7 AN9", "AP7 AR9 AT7 AU9 AV7 BB5 BD5 BF5")), ), - ("qsfp28", 0, + + # qsfp28 + ("qsfp28", 0, Subsignal("clk_n", Pins("K10")), Subsignal("clk_p", Pins("K11")), Subsignal("fs0", Pins("AT20"), IOStandard("LVCMOS12")), @@ -254,7 +289,7 @@ _io = [ Subsignal("txn", Pins("N8 M6 L8 K6")), Subsignal("txp", Pins("N9 M7 L9 K7")), ), - ("qsfp28", 1, + ("qsfp28", 1, Subsignal("clk_n", Pins("P10")), Subsignal("clk_p", Pins("P11")), Subsignal("fs0", Pins("AR22"), IOStandard("LVCMOS12")), @@ -270,22 +305,6 @@ _io = [ Subsignal("txn", Pins("U8 T6 R8 P6")), Subsignal("txp", Pins("U9 T7 R9 P7")), ), - ("serial", 0, - Subsignal("rx", Pins("BF18"), IOStandard("LVCMOS12")), - Subsignal("tx", Pins("BB20"), IOStandard("LVCMOS12")), - ), - ("serial_msp", 0, - Subsignal("rx", Pins("BA19"), IOStandard("LVCMOS12")), - Subsignal("tx", Pins("BB19"), IOStandard("LVCMOS12")), - ), - ("set_sw", 0, Pins("AL21")), - ("user_led", 0, Pins("BC21"), IOStandard("LVCMOS12")), - ("user_led", 1, Pins("BB21"), IOStandard("LVCMOS12")), - ("user_led", 2, Pins("BA20"), IOStandard("LVCMOS12")), - ("user_si570_clock", 0, - Subsignal("n", Pins("AV19"), IOStandard("DIFF_SSTL12")), - Subsignal("p", Pins("AU19"), IOStandard("DIFF_SSTL12")), - ), ] _connectors = [] diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py index 804fc69..7f827fc 100755 --- a/litex_boards/targets/alveo_u250.py +++ b/litex_boards/targets/alveo_u250.py @@ -17,6 +17,7 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser from litedram.modules import MTA18ASF2G72PZ from litedram.phy import usddrphy @@ -32,7 +33,7 @@ class _CRG(Module): # # # self.submodules.pll = pll = USMMCM(speedgrade=-2) - self.comb += pll.reset.eq(0) + self.comb += pll.reset.eq(0) # FIXME pll.register_clkin(platform.request("clk300", 0), 300e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) pll.create_clkout(self.cd_clk500, 500e6, with_reset=False) @@ -69,7 +70,6 @@ class BaseSoC(SoCCore): cmd_latency = 1, is_rdimm = True) self.add_csr("ddrphy") - self.add_constant("USDDRPHY_DEBUG") self.add_sdram("sdram", phy = self.ddrphy, module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"), @@ -80,20 +80,32 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) + # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------ self.add_ram("firmware_ram", 0x20000000, 0x8000) + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = Cat(*[platform.request("user_led", i) for i in range(3)]), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + # Build -------------------------------------------------------------------------------------------- def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Alveo U250") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main()