From ba017764321d7736ea6c381a5c30b8dfd2518f47 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 29 Mar 2021 15:28:04 +0200 Subject: [PATCH] targets/add_sdram: Simplify call by removing useless arguments. - main_ram mem_map is now directly used by add_sdram when origin is None. - max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can still be used enforced directly in the few cases it is useful. --- litex_boards/targets/camlink_4k.py | 11 +++--- litex_boards/targets/colorlight_5a_75x.py | 11 +++--- litex_boards/targets/colorlight_i5.py | 11 +++--- litex_boards/targets/digilent_arty.py | 11 +++--- litex_boards/targets/digilent_arty_s7.py | 11 +++--- litex_boards/targets/digilent_genesys2.py | 11 +++--- litex_boards/targets/digilent_nexys4ddr.py | 11 +++--- litex_boards/targets/digilent_nexys_video.py | 11 +++--- litex_boards/targets/enclustra_mercury_kx2.py | 11 +++--- litex_boards/targets/enclustra_mercury_xu5.py | 11 +++--- litex_boards/targets/fpc_iii.py | 11 +++--- litex_boards/targets/gsd_orangecrab.py | 11 +++--- litex_boards/targets/hackaday_hadbadge.py | 11 +++--- litex_boards/targets/kosagi_netv2.py | 11 +++--- litex_boards/targets/lambdaconcept_ecpix5.py | 11 +++--- .../targets/lattice_crosslink_nx_evn.py | 6 ++-- .../targets/lattice_crosslink_nx_vip.py | 6 ++-- litex_boards/targets/lattice_versa_ecp5.py | 11 +++--- litex_boards/targets/linsn_rv901t.py | 11 +++--- litex_boards/targets/logicbone.py | 11 +++--- litex_boards/targets/mist.py | 11 +++--- litex_boards/targets/numato_aller.py | 11 +++--- litex_boards/targets/numato_mimas_a7.py | 11 +++--- litex_boards/targets/numato_nereid.py | 11 +++--- litex_boards/targets/numato_tagus.py | 11 +++--- litex_boards/targets/qmtech_ep4ce15.py | 11 +++--- litex_boards/targets/qmtech_wukong.py | 11 +++--- litex_boards/targets/radiona_ulx3s.py | 12 +++---- litex_boards/targets/saanlima_pipistrello.py | 11 +++--- .../targets/scarabhardware_minispartan6.py | 12 +++---- litex_boards/targets/siglent_sds1104xe.py | 11 +++--- litex_boards/targets/sqrl_acorn.py | 11 +++--- litex_boards/targets/sqrl_xcu1525.py | 11 +++--- litex_boards/targets/terasic_de0nano.py | 11 +++--- litex_boards/targets/terasic_de10lite.py | 11 +++--- litex_boards/targets/terasic_de10nano.py | 11 +++--- litex_boards/targets/terasic_de1soc.py | 11 +++--- litex_boards/targets/terasic_de2_115.py | 11 +++--- litex_boards/targets/terasic_sockit.py | 34 +++++-------------- litex_boards/targets/trellisboard.py | 11 +++--- litex_boards/targets/trenz_c10lprefkit.py | 11 +++--- litex_boards/targets/trenz_tec0117.py | 1 - litex_boards/targets/xilinx_ac701.py | 11 +++--- litex_boards/targets/xilinx_alveo_u250.py | 11 +++--- litex_boards/targets/xilinx_alveo_u280.py | 11 +++--- litex_boards/targets/xilinx_kc705.py | 11 +++--- litex_boards/targets/xilinx_kcu105.py | 11 +++--- litex_boards/targets/xilinx_vc707.py | 11 +++--- litex_boards/targets/xilinx_vcu118.py | 11 +++--- litex_boards/targets/xilinx_zcu104.py | 11 +++--- litex_boards/targets/ztex213.py | 11 +++--- 51 files changed, 205 insertions(+), 361 deletions(-) diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index 93a61bd..822446f 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -92,13 +92,10 @@ class BaseSoC(SoCCore): sys_clk_freq=sys_clk_freq) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41K64M16(sys_clk_freq, "1:2"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT41K64M16(sys_clk_freq, "1:2"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Leds ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py index a5d4d80..424f660 100755 --- a/litex_boards/targets/colorlight_5a_75x.py +++ b/litex_boards/targets/colorlight_5a_75x.py @@ -152,13 +152,10 @@ class BaseSoC(SoCCore): sdram_cls = M12L16161A sdram_size = 0x40000000 self.add_sdram("sdram", - phy = self.sdrphy, - module = sdram_cls(sys_clk_freq, sdram_rate), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", sdram_size), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.sdrphy, + module = sdram_cls(sys_clk_freq, sdram_rate), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- diff --git a/litex_boards/targets/colorlight_i5.py b/litex_boards/targets/colorlight_i5.py index f97d306..c02c67a 100755 --- a/litex_boards/targets/colorlight_i5.py +++ b/litex_boards/targets/colorlight_i5.py @@ -132,13 +132,10 @@ class BaseSoC(SoCCore): # if board == "i5" and revision == "7.0": sdram_cls = M12L64322A # compat with EM638325-6H self.add_sdram("sdram", - phy = self.sdrphy, - module = sdram_cls(sys_clk_freq, sdram_rate), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.sdrphy, + module = sdram_cls(sys_clk_freq, sdram_rate), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- diff --git a/litex_boards/targets/digilent_arty.py b/litex_boards/targets/digilent_arty.py index 5160653..d02ce53 100755 --- a/litex_boards/targets/digilent_arty.py +++ b/litex_boards/targets/digilent_arty.py @@ -74,13 +74,10 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41K128M16(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT41K128M16(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- diff --git a/litex_boards/targets/digilent_arty_s7.py b/litex_boards/targets/digilent_arty_s7.py index 87f0733..e6c5e85 100755 --- a/litex_boards/targets/digilent_arty_s7.py +++ b/litex_boards/targets/digilent_arty_s7.py @@ -70,13 +70,10 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41K128M16(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT41K128M16(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Leds ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/digilent_genesys2.py b/litex_boards/targets/digilent_genesys2.py index 53ff10b..8964d31 100755 --- a/litex_boards/targets/digilent_genesys2.py +++ b/litex_boards/targets/digilent_genesys2.py @@ -66,13 +66,10 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41J256M16(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT41J256M16(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- diff --git a/litex_boards/targets/digilent_nexys4ddr.py b/litex_boards/targets/digilent_nexys4ddr.py index 8152978..c7aca50 100755 --- a/litex_boards/targets/digilent_nexys4ddr.py +++ b/litex_boards/targets/digilent_nexys4ddr.py @@ -73,13 +73,10 @@ class BaseSoC(SoCCore): nphases = 2, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT47H64M16(sys_clk_freq, "1:2"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT47H64M16(sys_clk_freq, "1:2"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- diff --git a/litex_boards/targets/digilent_nexys_video.py b/litex_boards/targets/digilent_nexys_video.py index 3f54df5..e969164 100755 --- a/litex_boards/targets/digilent_nexys_video.py +++ b/litex_boards/targets/digilent_nexys_video.py @@ -79,13 +79,10 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41K256M16(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT41K256M16(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet --------------------------------------------------------------------------------- diff --git a/litex_boards/targets/enclustra_mercury_kx2.py b/litex_boards/targets/enclustra_mercury_kx2.py index 21b851a..3c43be7 100755 --- a/litex_boards/targets/enclustra_mercury_kx2.py +++ b/litex_boards/targets/enclustra_mercury_kx2.py @@ -65,13 +65,10 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", - phy = self.ddrphy, - module = H5TC4G63CFR(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = H5TC4G63CFR(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Leds ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/enclustra_mercury_xu5.py b/litex_boards/targets/enclustra_mercury_xu5.py index 5d27f9a..2d8a50a 100755 --- a/litex_boards/targets/enclustra_mercury_xu5.py +++ b/litex_boards/targets/enclustra_mercury_xu5.py @@ -73,13 +73,10 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT40A256M16(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT40A256M16(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Leds ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/fpc_iii.py b/litex_boards/targets/fpc_iii.py index 15721d5..362067b 100755 --- a/litex_boards/targets/fpc_iii.py +++ b/litex_boards/targets/fpc_iii.py @@ -106,13 +106,10 @@ class BaseSoC(SoCCore): self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.comb += ddram.vccio.eq(Replicate(C(1), ddram.vccio.nbits)) self.add_sdram("sdram", - phy = self.ddrphy, - module = IS43TR16256A(sys_clk_freq, "1:2"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x20000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = IS43TR16256A(sys_clk_freq, "1:2"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) self.comb += platform.request("dram_vtt_en").eq(0 if self.integrated_main_ram_size else 1) diff --git a/litex_boards/targets/gsd_orangecrab.py b/litex_boards/targets/gsd_orangecrab.py index 9fea8f0..4489471 100755 --- a/litex_boards/targets/gsd_orangecrab.py +++ b/litex_boards/targets/gsd_orangecrab.py @@ -191,13 +191,10 @@ class BaseSoC(SoCCore): self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", - phy = self.ddrphy, - module = sdram_module(sys_clk_freq, "1:2"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = sdram_module(sys_clk_freq, "1:2"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Leds ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/hackaday_hadbadge.py b/litex_boards/targets/hackaday_hadbadge.py index b5aa61d..7ee67f1 100755 --- a/litex_boards/targets/hackaday_hadbadge.py +++ b/litex_boards/targets/hackaday_hadbadge.py @@ -72,13 +72,10 @@ class BaseSoC(SoCCore): if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", - phy = self.sdrphy, - module = AS4C32M8(sys_clk_freq, "1:1"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.sdrphy, + module = AS4C32M8(sys_clk_freq, "1:1"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/kosagi_netv2.py b/litex_boards/targets/kosagi_netv2.py index 781975e..6398e1f 100755 --- a/litex_boards/targets/kosagi_netv2.py +++ b/litex_boards/targets/kosagi_netv2.py @@ -80,13 +80,10 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", - phy = self.ddrphy, - module = K4B2G1646F(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = K4B2G1646F(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet --------------------------------------------------------------------------------- diff --git a/litex_boards/targets/lambdaconcept_ecpix5.py b/litex_boards/targets/lambdaconcept_ecpix5.py index 31d2d31..0d856a0 100755 --- a/litex_boards/targets/lambdaconcept_ecpix5.py +++ b/litex_boards/targets/lambdaconcept_ecpix5.py @@ -98,13 +98,10 @@ class BaseSoC(SoCCore): self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41K256M16(sys_clk_freq, "1:2"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT41K256M16(sys_clk_freq, "1:2"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- diff --git a/litex_boards/targets/lattice_crosslink_nx_evn.py b/litex_boards/targets/lattice_crosslink_nx_evn.py index c5b397d..e006281 100755 --- a/litex_boards/targets/lattice_crosslink_nx_evn.py +++ b/litex_boards/targets/lattice_crosslink_nx_evn.py @@ -64,9 +64,9 @@ class _CRG(Module): class BaseSoC(SoCCore): mem_map = { - "rom": 0x00000000, - "sram": 0x40000000, - "csr": 0xf0000000, + "rom" : 0x00000000, + "sram" : 0x40000000, + "csr" : 0xf0000000, } def __init__(self, sys_clk_freq=int(75e6), toolchain="radiant", **kwargs): platform = crosslink_nx_evn.Platform(toolchain=toolchain) diff --git a/litex_boards/targets/lattice_crosslink_nx_vip.py b/litex_boards/targets/lattice_crosslink_nx_vip.py index 13f6683..2e8e095 100755 --- a/litex_boards/targets/lattice_crosslink_nx_vip.py +++ b/litex_boards/targets/lattice_crosslink_nx_vip.py @@ -65,9 +65,9 @@ class _CRG(Module): class BaseSoC(SoCCore): mem_map = { - "rom": 0x00000000, - "sram": 0x40000000, - "csr": 0xf0000000, + "rom": 0x00000000, + "sram": 0x40000000, + "csr": 0xf0000000, } def __init__(self, sys_clk_freq=int(75e6), hyperram="none", toolchain="radiant", **kwargs): platform = crosslink_nx_vip.Platform(toolchain=toolchain) diff --git a/litex_boards/targets/lattice_versa_ecp5.py b/litex_boards/targets/lattice_versa_ecp5.py index 19d41d1..aeffff7 100755 --- a/litex_boards/targets/lattice_versa_ecp5.py +++ b/litex_boards/targets/lattice_versa_ecp5.py @@ -102,13 +102,10 @@ class BaseSoC(SoCCore): self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41K64M16(sys_clk_freq, "1:2"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT41K64M16(sys_clk_freq, "1:2"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py index 4726555..b93ad79 100755 --- a/litex_boards/targets/linsn_rv901t.py +++ b/litex_boards/targets/linsn_rv901t.py @@ -66,13 +66,10 @@ class BaseSoC(SoCCore): if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", - phy = self.sdrphy, - module = M12L64322A(sys_clk_freq, "1:1"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.sdrphy, + module = M12L64322A(sys_clk_freq, "1:1"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet --------------------------------------------------------------------------------- diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py index 9053dd6..56316af 100755 --- a/litex_boards/targets/logicbone.py +++ b/litex_boards/targets/logicbone.py @@ -128,13 +128,10 @@ class BaseSoC(SoCCore): self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", - phy = self.ddrphy, - module = sdram_module(sys_clk_freq, "1:2"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = sdram_module(sys_clk_freq, "1:2"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet --------------------------------------------------------------------------------- diff --git a/litex_boards/targets/mist.py b/litex_boards/targets/mist.py index 609a5f1..a1e240e 100755 --- a/litex_boards/targets/mist.py +++ b/litex_boards/targets/mist.py @@ -70,13 +70,10 @@ class BaseSoC(SoCCore): if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", - phy = self.sdrphy, - module = MT48LC16M16(sys_clk_freq, "1:1"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x2000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.sdrphy, + module = MT48LC16M16(sys_clk_freq, "1:1"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Video Terminal --------------------------------------------------------------------------- diff --git a/litex_boards/targets/numato_aller.py b/litex_boards/targets/numato_aller.py index dcbd7db..b668659 100755 --- a/litex_boards/targets/numato_aller.py +++ b/litex_boards/targets/numato_aller.py @@ -76,13 +76,10 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41J128M16(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT41J128M16(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # PCIe ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/numato_mimas_a7.py b/litex_boards/targets/numato_mimas_a7.py index 01fcf19..3efa42c 100755 --- a/litex_boards/targets/numato_mimas_a7.py +++ b/litex_boards/targets/numato_mimas_a7.py @@ -70,13 +70,10 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41J128M16(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT41J128M16(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet --------------------------------------------------------------------------------- diff --git a/litex_boards/targets/numato_nereid.py b/litex_boards/targets/numato_nereid.py index 01e9ed6..89cebf4 100755 --- a/litex_boards/targets/numato_nereid.py +++ b/litex_boards/targets/numato_nereid.py @@ -73,13 +73,10 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # PCIe ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/numato_tagus.py b/litex_boards/targets/numato_tagus.py index 8318fe9..17db2fd 100755 --- a/litex_boards/targets/numato_tagus.py +++ b/litex_boards/targets/numato_tagus.py @@ -77,13 +77,10 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41J128M16(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT41J128M16(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # PCIe ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/qmtech_ep4ce15.py b/litex_boards/targets/qmtech_ep4ce15.py index 5ea64e4..4eebfb2 100755 --- a/litex_boards/targets/qmtech_ep4ce15.py +++ b/litex_boards/targets/qmtech_ep4ce15.py @@ -76,13 +76,10 @@ class BaseSoC(SoCCore): sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", - phy = self.sdrphy, - module = IS42S16160(sys_clk_freq, sdram_rate), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.sdrphy, + module = IS42S16160(sys_clk_freq, sdram_rate), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Leds ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/qmtech_wukong.py b/litex_boards/targets/qmtech_wukong.py index 7eb4945..26bf945 100755 --- a/litex_boards/targets/qmtech_wukong.py +++ b/litex_boards/targets/qmtech_wukong.py @@ -72,13 +72,10 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41K128M16(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT41K128M16(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- diff --git a/litex_boards/targets/radiona_ulx3s.py b/litex_boards/targets/radiona_ulx3s.py index b06b424..6969d34 100755 --- a/litex_boards/targets/radiona_ulx3s.py +++ b/litex_boards/targets/radiona_ulx3s.py @@ -113,13 +113,11 @@ class BaseSoC(SoCCore): sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", - phy = self.sdrphy, - module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = False + phy = self.sdrphy, + module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_reverse = False ) # Video ------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/saanlima_pipistrello.py b/litex_boards/targets/saanlima_pipistrello.py index 74cd6e6..9174577 100755 --- a/litex_boards/targets/saanlima_pipistrello.py +++ b/litex_boards/targets/saanlima_pipistrello.py @@ -179,13 +179,10 @@ class BaseSoC(SoCCore): self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ] self.add_sdram("sdram", - phy = self.ddrphy, - module = MT46H32M16(sys_clk_freq, "1:2"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT46H32M16(sys_clk_freq, "1:2"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Leds ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/scarabhardware_minispartan6.py b/litex_boards/targets/scarabhardware_minispartan6.py index 9ea2727..a090bc1 100755 --- a/litex_boards/targets/scarabhardware_minispartan6.py +++ b/litex_boards/targets/scarabhardware_minispartan6.py @@ -85,13 +85,11 @@ class BaseSoC(SoCCore): sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", - phy = self.sdrphy, - module = AS4C16M16(sys_clk_freq, sdram_rate), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = False + phy = self.sdrphy, + module = AS4C16M16(sys_clk_freq, sdram_rate), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_reverse = False ) # Video ------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/siglent_sds1104xe.py b/litex_boards/targets/siglent_sds1104xe.py index 78ba166..e7b6e8f 100755 --- a/litex_boards/targets/siglent_sds1104xe.py +++ b/litex_boards/targets/siglent_sds1104xe.py @@ -88,13 +88,10 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41K64M16(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT41K64M16(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Etherbone -------------------------------------------------------------------------------- diff --git a/litex_boards/targets/sqrl_acorn.py b/litex_boards/targets/sqrl_acorn.py index dbe32d5..3fdbe2e 100755 --- a/litex_boards/targets/sqrl_acorn.py +++ b/litex_boards/targets/sqrl_acorn.py @@ -92,13 +92,10 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41K512M16(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT41K512M16(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # PCIe ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/sqrl_xcu1525.py b/litex_boards/targets/sqrl_xcu1525.py index c26a87e..9e2907d 100755 --- a/litex_boards/targets/sqrl_xcu1525.py +++ b/litex_boards/targets/sqrl_xcu1525.py @@ -77,13 +77,10 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT40A512M8(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT40A512M8(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions. platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]") diff --git a/litex_boards/targets/terasic_de0nano.py b/litex_boards/targets/terasic_de0nano.py index 54887fb..4fc12c4 100755 --- a/litex_boards/targets/terasic_de0nano.py +++ b/litex_boards/targets/terasic_de0nano.py @@ -76,13 +76,10 @@ class BaseSoC(SoCCore): sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", - phy = self.sdrphy, - module = IS42S16160(sys_clk_freq, sdram_rate), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.sdrphy, + module = IS42S16160(sys_clk_freq, sdram_rate), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Leds ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/terasic_de10lite.py b/litex_boards/targets/terasic_de10lite.py index 2bb6e38..53709e6 100755 --- a/litex_boards/targets/terasic_de10lite.py +++ b/litex_boards/targets/terasic_de10lite.py @@ -70,13 +70,10 @@ class BaseSoC(SoCCore): if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", - phy = self.sdrphy, - module = IS42S16320(sys_clk_freq, "1:1"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.sdrphy, + module = IS42S16320(sys_clk_freq, "1:1"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Video Terminal --------------------------------------------------------------------------- diff --git a/litex_boards/targets/terasic_de10nano.py b/litex_boards/targets/terasic_de10nano.py index 1f1f3b7..6f872e8 100755 --- a/litex_boards/targets/terasic_de10nano.py +++ b/litex_boards/targets/terasic_de10nano.py @@ -81,13 +81,10 @@ class BaseSoC(SoCCore): sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", - phy = self.sdrphy, - module = AS4C32M16(sys_clk_freq, sdram_rate), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.sdrphy, + module = AS4C32M16(sys_clk_freq, sdram_rate), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Video Terminal --------------------------------------------------------------------------- diff --git a/litex_boards/targets/terasic_de1soc.py b/litex_boards/targets/terasic_de1soc.py index 89acd80..e0c0383 100755 --- a/litex_boards/targets/terasic_de1soc.py +++ b/litex_boards/targets/terasic_de1soc.py @@ -65,13 +65,10 @@ class BaseSoC(SoCCore): if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", - phy = self.sdrphy, - module = IS42S16320(sys_clk_freq, "1:1"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.sdrphy, + module = IS42S16320(sys_clk_freq, "1:1"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/terasic_de2_115.py b/litex_boards/targets/terasic_de2_115.py index 8e65a73..d3d0caf 100755 --- a/litex_boards/targets/terasic_de2_115.py +++ b/litex_boards/targets/terasic_de2_115.py @@ -65,13 +65,10 @@ class BaseSoC(SoCCore): if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", - phy = self.sdrphy, - module = IS42S16320(self.clk_freq, "1:1"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.sdrphy, + module = IS42S16320(self.clk_freq, "1:1"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/terasic_sockit.py b/litex_boards/targets/terasic_sockit.py index ef7bfd2..e312bd0 100755 --- a/litex_boards/targets/terasic_sockit.py +++ b/litex_boards/targets/terasic_sockit.py @@ -120,31 +120,15 @@ class BaseSoC(SoCCore): self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- - if mister_sdram == "xs_v22": - sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY - self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) - self.add_sdram("sdram", - phy = self.sdrphy, - module = W9825G6KH6(sys_clk_freq, sdram_rate), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True - ) - - if mister_sdram == "xs_v24": - sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY - self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) - self.add_sdram("sdram", - phy = self.sdrphy, - module = AS4C32M16(sys_clk_freq, sdram_rate), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True - ) + sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY + sdrphy_mod = {"xs_v22": W9825G6KH6, "xs_v24": AS4C32M16} + self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) + self.add_sdram("sdram", + phy = self.sdrphy, + module = sdrphy_mod(sys_clk_freq, sdram_rate), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) + ) # Video Terminal --------------------------------------------------------------------------- if with_video_terminal: diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index 88c7c6b..f679212 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -132,13 +132,10 @@ class BaseSoC(SoCCore): self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41J256M16(sys_clk_freq, "1:2"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT41J256M16(sys_clk_freq, "1:2"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet --------------------------------------------------------------------------------- diff --git a/litex_boards/targets/trenz_c10lprefkit.py b/litex_boards/targets/trenz_c10lprefkit.py index 7a6e045..2db242c 100755 --- a/litex_boards/targets/trenz_c10lprefkit.py +++ b/litex_boards/targets/trenz_c10lprefkit.py @@ -79,13 +79,10 @@ class BaseSoC(SoCCore): if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", - phy = self.sdrphy, - module = MT48LC16M16(sys_clk_freq, "1:1"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.sdrphy, + module = MT48LC16M16(sys_clk_freq, "1:1"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet --------------------------------------------------------------------------------- diff --git a/litex_boards/targets/trenz_tec0117.py b/litex_boards/targets/trenz_tec0117.py index 40e1173..90b7ea3 100755 --- a/litex_boards/targets/trenz_tec0117.py +++ b/litex_boards/targets/trenz_tec0117.py @@ -111,7 +111,6 @@ class BaseSoC(SoCCore): self.add_sdram("sdram", phy = self.sdrphy, module = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME. - origin = self.mem_map["main_ram"], l2_cache_size = 128, l2_cache_min_data_width = 256, ) diff --git a/litex_boards/targets/xilinx_ac701.py b/litex_boards/targets/xilinx_ac701.py index 21b4b23..e137661 100755 --- a/litex_boards/targets/xilinx_ac701.py +++ b/litex_boards/targets/xilinx_ac701.py @@ -76,13 +76,10 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT8JTF12864(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT8JTF12864(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet --------------------------------------------------------------------------------- diff --git a/litex_boards/targets/xilinx_alveo_u250.py b/litex_boards/targets/xilinx_alveo_u250.py index 1c0e177..7214578 100755 --- a/litex_boards/targets/xilinx_alveo_u250.py +++ b/litex_boards/targets/xilinx_alveo_u250.py @@ -78,13 +78,10 @@ class BaseSoC(SoCCore): iodelay_clk_freq = 500e6, is_rdimm = True) self.add_sdram("sdram", - phy = self.ddrphy, - module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------ diff --git a/litex_boards/targets/xilinx_alveo_u280.py b/litex_boards/targets/xilinx_alveo_u280.py index 24ef2d3..2a63afc 100755 --- a/litex_boards/targets/xilinx_alveo_u280.py +++ b/litex_boards/targets/xilinx_alveo_u280.py @@ -77,13 +77,10 @@ class BaseSoC(SoCCore): iodelay_clk_freq = 500e6, is_rdimm = True) self.add_sdram("sdram", - phy = self.ddrphy, - module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------ diff --git a/litex_boards/targets/xilinx_kc705.py b/litex_boards/targets/xilinx_kc705.py index 7e494d8..535e966 100755 --- a/litex_boards/targets/xilinx_kc705.py +++ b/litex_boards/targets/xilinx_kc705.py @@ -71,13 +71,10 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT8JTF12864(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT8JTF12864(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet --------------------------------------------------------------------------------- diff --git a/litex_boards/targets/xilinx_kcu105.py b/litex_boards/targets/xilinx_kcu105.py index b0af4fc..3ba9a5e 100755 --- a/litex_boards/targets/xilinx_kcu105.py +++ b/litex_boards/targets/xilinx_kcu105.py @@ -80,13 +80,10 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) self.add_sdram("sdram", - phy = self.ddrphy, - module = EDY4016A(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = EDY4016A(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- diff --git a/litex_boards/targets/xilinx_vc707.py b/litex_boards/targets/xilinx_vc707.py index d8e1680..dc74bcd 100755 --- a/litex_boards/targets/xilinx_vc707.py +++ b/litex_boards/targets/xilinx_vc707.py @@ -67,13 +67,10 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT8JTF12864(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT8JTF12864(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # PCIe ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/xilinx_vcu118.py b/litex_boards/targets/xilinx_vcu118.py index f85d0a7..bd282eb 100755 --- a/litex_boards/targets/xilinx_vcu118.py +++ b/litex_boards/targets/xilinx_vcu118.py @@ -74,13 +74,10 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6) self.add_sdram("sdram", - phy = self.ddrphy, - module = EDY4016A(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = EDY4016A(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Leds ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/xilinx_zcu104.py b/litex_boards/targets/xilinx_zcu104.py index 8b98948..e8e3cc7 100755 --- a/litex_boards/targets/xilinx_zcu104.py +++ b/litex_boards/targets/xilinx_zcu104.py @@ -75,13 +75,10 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6) self.add_sdram("sdram", - phy = self.ddrphy, - module = MTA4ATF51264HZ(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MTA4ATF51264HZ(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Leds ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/ztex213.py b/litex_boards/targets/ztex213.py index afe1f1d..dcfa933 100755 --- a/litex_boards/targets/ztex213.py +++ b/litex_boards/targets/ztex213.py @@ -83,13 +83,10 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41J128M16(sys_clk_freq, "1:4"), #MT41J128M16XX-125 - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True + phy = self.ddrphy, + module = MT41J128M16(sys_clk_freq, "1:4"), #MT41J128M16XX-125 + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) ) # Leds -------------------------------------------------------------------------------------