From ba8321a3abfbb3b65118f35d967f5bf6d7454715 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 14 Jul 2021 10:02:58 +0200 Subject: [PATCH] trenz_tec0117: Use new DDROutput to generate SDRAM Clk. --- litex_boards/targets/trenz_tec0117.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/trenz_tec0117.py b/litex_boards/targets/trenz_tec0117.py index a934638..28653a2 100755 --- a/litex_boards/targets/trenz_tec0117.py +++ b/litex_boards/targets/trenz_tec0117.py @@ -13,7 +13,7 @@ import importlib from migen import * -from litex.build.io import CRG +from litex.build.io import DDROutput from litex.soc.cores.clock.gowin_gw1n import GW1NPLL from litex.soc.integration.soc_core import * @@ -100,7 +100,7 @@ class BaseSoC(SoCCore): self.dq = platform.request("IO_sdram_dq") sdram_pads = SDRAMPads() - self.comb += sdram_pads.clk.eq(~ClockSignal("sys")) # FIXME: use phase shift from PLL. + self.specials += DDROutput(0, 1, sdram_pads.clk, ClockSignal("sys")) # FIXME: use phase shift from PLL. sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq)