From bb974ae1af77753443c41ea0af47b627b251feaf Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 23 Mar 2022 15:19:40 +0100
Subject: [PATCH] decklink_quad_hdmi_recorder: Add pcie_lanes parameter and
 4x/8x support.

---
 litex_boards/targets/decklink_quad_hdmi_recorder.py | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/litex_boards/targets/decklink_quad_hdmi_recorder.py b/litex_boards/targets/decklink_quad_hdmi_recorder.py
index d0845e4..fe07448 100755
--- a/litex_boards/targets/decklink_quad_hdmi_recorder.py
+++ b/litex_boards/targets/decklink_quad_hdmi_recorder.py
@@ -58,7 +58,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(200e6), with_pcie=False, **kwargs):
+    def __init__(self, sys_clk_freq=int(200e6), with_pcie=False, pcie_lanes=4, **kwargs):
         platform = quad_hdmi_recorder.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -87,10 +87,16 @@ class BaseSoC(SoCCore):
             )
 
         # PCIe -------------------------------------------------------------------------------------
+        # FIXME: Does not seem to be working when also enabling DRAM. Has been tested succesfully by
+        # disabling DRAM with --integrated-main-ram-size=0x100.
         if with_pcie:
-            self.submodules.pcie_phy = USPCIEPHY(platform, platform.request("pcie_x4"),
+            data_width = {
+                4 : 128,
+                8 : 256,
+            }[pcie_lanes]
+            self.submodules.pcie_phy = USPCIEPHY(platform, platform.request(f"pcie_x{pcie_lanes}"),
                 speed      = "gen3",
-                data_width = 128,
+                data_width = data_width,
                 bar0_size  = 0x20000)
             self.add_pcie(phy=self.pcie_phy, ndmas=1)
             # False Paths (FIXME: Improve integration).