diff --git a/litex_boards/platforms/arrow_sockit.py b/litex_boards/platforms/arrow_sockit.py new file mode 100644 index 0000000..e90e6a1 --- /dev/null +++ b/litex_boards/platforms/arrow_sockit.py @@ -0,0 +1,169 @@ +# +# This file is part of LiteX-Boards. +# +# I (HB) used the similar de1soc board as a starting point, therefore: +# Copyright (c) 2019 Antony Pavlov +# SocKit adaption (c) 2020 Hans Baier +# +# SPDX-License-Identifier: BSD-2-Clause + +from litex.build.altera import AlteraPlatform +from litex.build.altera.programmer import USBBlaster +from litex.build.generic_platform import Pins, IOStandard, Subsignal, Misc + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # Clk + ("clk50", 0, Pins("AF14"), IOStandard("3.3-V LVTTL")), + + # Leds + ("user_led", 0, Pins("AF10"), IOStandard("3.3-V LVTTL")), + ("user_led", 1, Pins("AD10"), IOStandard("3.3-V LVTTL")), + ("user_led", 2, Pins("AE11"), IOStandard("3.3-V LVTTL")), + ("user_led", 3, Pins("AD7"), IOStandard("3.3-V LVTTL")), + + # Buttons + ("user_btn", 0, Pins("AE9"), IOStandard("3.3-V LVTTL")), + ("user_btn", 1, Pins("AE12"), IOStandard("3.3-V LVTTL")), + ("user_btn", 2, Pins("AD9"), IOStandard("3.3-V LVTTL")), + ("user_btn", 3, Pins("AD11"), IOStandard("3.3-V LVTTL")), + + # Switches + ("user_sw", 0, Pins("W25"), IOStandard("3.3-V LVTTL")), + ("user_sw", 1, Pins("V25"), IOStandard("3.3-V LVTTL")), + ("user_sw", 2, Pins("AC28"), IOStandard("3.3-V LVTTL")), + ("user_sw", 3, Pins("AC29"), IOStandard("3.3-V LVTTL")), + + # DDR3 SDRAM + ("ddram", 0, + Subsignal("a", Pins( + "AJ14 AK14 AH12 AJ12 AG15 AH15 AK12 AK13", + "AH13 AH14 AJ9 AK9 AK7 AK8 AG12"), + IOStandard("SSTL15"), + Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT") + ), + Subsignal("ba", Pins("AH10 AJ11 AK11"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), + Subsignal("ras_n", Pins("AH8"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), + Subsignal("cas_n", Pins("AH7"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), + Subsignal("we_n", Pins("AJ6"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), + Subsignal("dm", Pins("AH17 AG23 AK23 AJ27"), + IOStandard("SSTL-15 CLASS I"), + Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION") + ), + Subsignal("dq", Pins( + "AF18 AE17 AG16 AF16 AH20 AG21 AJ16 AH18", + "AK18 AJ17 AG18 AK19 AG20 AF19 AJ20 AH24", + "AE19 AE18 AG22 AK22 AF21 AF20 AH23 AK24", + "AF24 AF23 AJ24 AK26 AE23 AE22 AG25 AK27"), + IOStandard("SSTL-15 CLASS I"), + Misc("INPUT_TERMINATION=PARALLEL 50 OHM WITH CALIBRATION"), + Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION"), + ), + Subsignal("dqs_p", Pins("V16 V17 Y17 AC20"), + IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"), + Misc("INPUT_TERMINATION=PARALLEL 50 OHM WITH CALIBRATION"), + Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION") + ), + Subsignal("dqs_n", Pins("W16 W17 AA18 AD19"), + IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"), + Misc("INPUT_TERMINATION=PARALLEL 50 OHM WITH CALIBRATION"), + Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION") + ), + Subsignal("clk_p", Pins("AA14"), + IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"), + Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION"), + Misc("D5_DELAY=2") + ), + Subsignal("clk_n", Pins("AA15"), + IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"), + Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION"), + Misc("D5_DELAY=2") + ), + Subsignal("cs_n", Pins("AB15"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), + Subsignal("cke", Pins("AJ21"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), + Subsignal("odt", Pins("AE16"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), + Subsignal("reset_n", Pins("AK21"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), + Subsignal("rzq", Pins("AG1"), IOStandard("SSTL-15")), + ), + + # VGA + ("vga", 0, + Subsignal("hsync_n", Pins("AD12")), + Subsignal("vsync_n", Pins("AC12")), + Subsignal("sync_n", Pins("AG2")), + Subsignal("blank_n", Pins("AH3")), + Subsignal("r", Pins("AG5 AA12 AB12 AF6 AG6 AJ2 AH5 AJ1")), + Subsignal("g", Pins("Y21 AA25 AB26 AB22 AB23 AA24 AB25 AE27")), + Subsignal("b", Pins("AE28 Y23 Y24 AG28 AF28 V23 W24 AF29")), + IOStandard("3.3-V LVTTL") + ), + + ("irda", 0, + Subsignal("irda_rxd", Pins("AH2")), + IOStandard("3.3-V LVTTL") + ), + + ("temperature", 0, + Subsignal("temp_cs_n", Pins("AF8")), + Subsignal("temp_din", Pins("AG7")), + Subsignal("temp_dout", Pins("AG1")), + Subsignal("temp_sclk", Pins("AF9")), + IOStandard("3.3-V LVTTL") + ), + + ("audio", 0, + Subsignal("aud_adclrck", Pins("AG30")), + Subsignal("aud_adcdat", Pins("AC27")), + Subsignal("aud_daclrck", Pins("AH4")), + Subsignal("aud_dacdat", Pins("AG3")), + Subsignal("aud_xck", Pins("AC9")), + Subsignal("aud_bclk", Pins("AE7")), + Subsignal("aud_i2c_sclk", Pins("AH30")), + Subsignal("aud_i2c_sdat", Pins("AF30")), + Subsignal("aud_mute", Pins("AD26")), + IOStandard("3.3-V LVTTL") + ) +] + +_connectors_hsmc_gpio_daughterboard = [ + ("J2", "G15 F14 H15 F15 A13 G13 B13 H14 B11 E13 - - " + + "C12 F13 B8 B12 C8 C13 A10 D10 A11 D11 B7 D12 C7 E12 A5 D9 - - " + + "A6 E9 A3 B5 A4 B6 B1 C2 B2 D2"), + ("J2p", "D1 E1 E11 F11"), # top to bottom, starting with 57 + + ("J3", "AB27 F8 AA26 F9 B3 G8 C3 H8 D4 H7 - - " + + "E4 J7 E2 K8 E3 K7 E6 J9 E7 J10 C4 J12 D5 G10 C5 J12 - - " + + "D6 K12 F6 G11 G7 G12 D7 A8 E8 A9"), + ("J3p", "C9 C10 H12 H13"), # top to bottom, starting with 117 + + ("J4", "- - AD3 AE1 AD4 AE2 - - AB3 AC1 - - " + + "AB4 AC2 - - Y3 AA1 Y4 AA2 - - V3 W1 V4 W2 - - - -" + + "T3 U1 T4 R1 - R2 P3 U2 P4 -"), + ("J4p", "M3 M4 - H3 H4 J14 AD29 - N1 N2 - J1 J2") # top to bottom, starting with 169 +] + +# Platform ----------------------------------------------------------------------------------------- + +_device_map = { + "revB/C": "5CSXFC6D6F31C8ES", + "revD": "5CSXFC6D6F31C8", +} + +class Platform(AlteraPlatform): + default_clk_name = "clk50" + default_clk_period = 1e9/50e6 + + def __init__(self, revision="revB/C"): + assert revision in _device_map.keys() + self.revision = revision + + # Yes, the HSMC GPIO board is optional, but only it has generic connectors + AlteraPlatform.__init__(self, _device_map[revision], _io, connectors=_connectors_hsmc_gpio_daughterboard) + + def create_programmer(self): + return USBBlaster() + + def do_finalize(self, fragment): + AlteraPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6) diff --git a/litex_boards/platforms/de0nano.py b/litex_boards/platforms/de0nano.py index 4470052..b58b0fc 100644 --- a/litex_boards/platforms/de0nano.py +++ b/litex_boards/platforms/de0nano.py @@ -117,6 +117,14 @@ _io = [ ), ] +# this is partly redundant to the above, but convenient if you plug in your own peripherals +_connectors = [ + # PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 + ("JP1", "A8 D3 B8 C3 A2 A3 B3 B4 A4 B5 - - A5 D5 B6 A6 B7 D6 A7 C6 C8 E6 E7 D8 E8 F8 F9 E9 - - C9 D9 E11 E10 C11 B11 A12 D11 D12 B12"), + ("JP2", "T9 F13 R9 T15 T14 T13 R13 T12 R12 T11 - - T10 R11 P11 R10 N12 P9 N9 N11 L16 K16 R16 L15 P15 P16 R14 N16 - - N15 P14 L14 N14 M10 L13 J16 K15 J13 J14"), + ("JP3", "- E15 E16 M16 A14 B16 C14 C16 C15 D16 D15 D14 F15 F16 F14 G16 G15 - - - - - - - - -") +] + # Platform ----------------------------------------------------------------------------------------- class Platform(AlteraPlatform): @@ -124,7 +132,7 @@ class Platform(AlteraPlatform): default_clk_period = 1e9/50e6 def __init__(self): - AlteraPlatform.__init__(self, "EP4CE22F17C6", _io) + AlteraPlatform.__init__(self, "EP4CE22F17C6", _io, _connectors) def create_programmer(self): return USBBlaster() diff --git a/litex_boards/targets/arrow_sockit.py b/litex_boards/targets/arrow_sockit.py new file mode 100755 index 0000000..030e8d1 --- /dev/null +++ b/litex_boards/targets/arrow_sockit.py @@ -0,0 +1,98 @@ +#!/usr/bin/env python3 +# +# This file is part of LiteX-Boards. +# +# I (HB) used the similar de1soc board as a starting point, therefore: +# Copyright (c) 2019 Antony Pavlov +# SocKit adaption (c) 2020 Hans Baier +# +# SPDX-License-Identifier: BSD-2-Clause + +import os +import argparse + +from migen.fhdl.module import Module +from migen.fhdl.structure import Signal, ClockDomain +from migen.genlib.resetsync import AsyncResetSynchronizer + +from litex.build.io import DDROutput +from litex.soc.cores.clock import CycloneVPLL +from litex.soc.integration.builder import Builder, builder_args, builder_argdict +from litex.soc.integration.soc_core import SoCCore +from litex.soc.integration.soc_sdram import soc_sdram_argdict, soc_sdram_args +from litex.soc.cores.led import LedChaser + +from litex_boards.platforms import arrow_sockit + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq): + self.rst = Signal() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) + + # Clk / Rst + clk50 = platform.request("clk50") + + # PLL + self.submodules.pll = pll = CycloneVPLL(speedgrade="-C6") + self.comb += pll.reset.eq(self.rst) + pll.register_clkin(clk50, 50e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(50e6), revisionD=False, **kwargs): + revision = "revD" if revisionD else "revB/C" + platform = arrow_sockit.Platform(revision) + + # Defaults to Crossover UART, because Serial is attached to the HPS + # and thus not available to the FPGA + if kwargs["uart_name"] == "serial": + kwargs["uart_name"] = "crossover" + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on the Arrow SoCKit", + ident_version = True, + **kwargs) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq) + + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + + +# Build -------------------------------------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on SoCKit") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--revisionD", action="store_true", help="board revision D, otherwise the more widespread revision B/C is assumed") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") + builder_args(parser) + soc_sdram_args(parser) + args = parser.parse_args() + + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + revisionD = args.revisionD, + **soc_sdram_argdict(args) + ) + builder = Builder(soc, **builder_argdict(args)) + builder.build(run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof")) + +if __name__ == "__main__": + main()