From bc3c42ab5f42e34a8b53db7089d424aebe5e4bb9 Mon Sep 17 00:00:00 2001
From: Ilia Sergachev <ilia@sergachev.ch>
Date: Wed, 22 Dec 2021 03:27:30 +0100
Subject: [PATCH] zedboard: disable soc uart for all variants (zynq does not
 need it, for soft cpus there are no pins)

---
 litex_boards/targets/digilent_zedboard.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex_boards/targets/digilent_zedboard.py b/litex_boards/targets/digilent_zedboard.py
index 9b9d497..eba47c7 100644
--- a/litex_boards/targets/digilent_zedboard.py
+++ b/litex_boards/targets/digilent_zedboard.py
@@ -53,7 +53,6 @@ class BaseSoC(SoCCore):
 
         if kwargs.get("cpu_type", None) == "zynq7000":
             kwargs['integrated_sram_size'] = 0
-            kwargs['with_uart'] = False
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
@@ -159,6 +158,7 @@ def main():
     soc_core_args(parser)
     vivado_build_args(parser)
     parser.set_defaults(cpu_type="zynq7000")
+    parser.set_defaults(no_uart=True)
     args = parser.parse_args()
 
     soc = BaseSoC(