diff --git a/litex_boards/platforms/digilent_cmod_a7.py b/litex_boards/platforms/digilent_cmod_a7.py
index 2b7de21..09e1280 100644
--- a/litex_boards/platforms/digilent_cmod_a7.py
+++ b/litex_boards/platforms/digilent_cmod_a7.py
@@ -63,8 +63,11 @@ class Platform(XilinxPlatform):
     default_clk_name   = "clk12"
     default_clk_period = 1e9/12e6
 
-    def __init__(self):
-        XilinxPlatform.__init__(self, "xc7a35t-cpg236-1", _io, _connectors, toolchain="vivado")
+    def __init__(self, variant="a7-35", toolchain="vivado"):
+        device = {
+                "a7-35": "xc7a35t-cpg236-1"
+                }[variant]
+        XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
 
     def do_finalize(self,fragment):
         XilinxPlatform.do_finalize(self, fragment)