diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py index 93eb276..c4085ff 100755 --- a/litex_boards/targets/ac701.py +++ b/litex_boards/targets/ac701.py @@ -132,10 +132,10 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on AC701") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") - parser.add_argument("--ethernet-phy", default="rgmii", help="Select Ethernet PHY (rgmii or 1000basex)") + parser.add_argument("--ethernet-phy", default="rgmii", help="Select Ethernet PHY: rgmii (default) or 1000basex") args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, ethernet_phy=args.ethernet_phy, **soc_sdram_argdict(args)) diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py index b2b774d..43769e9 100755 --- a/litex_boards/targets/acorn_cle_215.py +++ b/litex_boards/targets/acorn_cle_215.py @@ -165,7 +165,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Acorn CLE 215+") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") - parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires adapter off P2)") + parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires SDCard adapter on P2)") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--flash", action="store_true", help="Flash bitstream") diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py index 2dc1e46..677946d 100755 --- a/litex_boards/targets/alveo_u250.py +++ b/litex_boards/targets/alveo_u250.py @@ -142,10 +142,10 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Alveo U250") - parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py index f82f729..d43c5a9 100755 --- a/litex_boards/targets/arty.py +++ b/litex_boards/targets/arty.py @@ -104,15 +104,15 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - builder_args(parser) - soc_sdram_args(parser) - vivado_build_args(parser) + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") + builder_args(parser) + soc_sdram_args(parser) + vivado_build_args(parser) args = parser.parse_args() assert not (args.with_ethernet and args.with_etherbone) diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py index 1d6b152..843bc6b 100755 --- a/litex_boards/targets/c10lprefkit.py +++ b/litex_boards/targets/c10lprefkit.py @@ -107,11 +107,11 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on C10 LP RefKit") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index 4f12909..08d9c7b 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -113,9 +113,9 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Cam Link 4K") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py index e9a1563..df27a1e 100755 --- a/litex_boards/targets/colorlight_5a_75x.py +++ b/litex_boards/targets/colorlight_5a_75x.py @@ -175,19 +175,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight 5A-75X") - builder_args(parser) - soc_core_args(parser) - trellis_args(parser) parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--board", default="5a-75b", help="Board type: 5a-75b (default) or 5a-75e") - parser.add_argument("--revision", default="7.0", type=str, help="Board revision 7.0 (default), 6.0 or 6.1") + parser.add_argument("--revision", default="7.0", type=str, help="Board revision: 7.0 (default), 6.0 or 6.1") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") - parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)") - parser.add_argument("--sys-clk-freq", default=60e6, type=float, help="System clock frequency (default=60MHz)") + parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1") + parser.add_argument("--sys-clk-freq", default=60e6, type=float, help="System clock frequency (default: 60MHz)") parser.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator") - parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate") + parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate") + builder_args(parser) + soc_core_args(parser) + trellis_args(parser) args = parser.parse_args() assert not (args.with_ethernet and args.with_etherbone) diff --git a/litex_boards/targets/crosslink_nx_evn.py b/litex_boards/targets/crosslink_nx_evn.py index e739652..df6c3e2 100755 --- a/litex_boards/targets/crosslink_nx_evn.py +++ b/litex_boards/targets/crosslink_nx_evn.py @@ -102,11 +102,11 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Crosslink-NX Eval Board") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") - parser.add_argument("--serial", default="serial", help="UART Pins: serial (requires R15 and R17 to be soldered) or serial_pmod[0-2] (default=serial)") - parser.add_argument("--prog-target", default="direct", help="Programming Target: direct or flash") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") + parser.add_argument("--serial", default="serial", help="UART Pins: serial (default, requires R15 and R17 to be soldered) or serial_pmod[0-2]") + parser.add_argument("--prog-target", default="direct", help="Programming Target: direct or flash") builder_args(parser) soc_core_args(parser) args = parser.parse_args() diff --git a/litex_boards/targets/crosslink_nx_vip.py b/litex_boards/targets/crosslink_nx_vip.py index fa032ff..7d50aaf 100755 --- a/litex_boards/targets/crosslink_nx_vip.py +++ b/litex_boards/targets/crosslink_nx_vip.py @@ -107,11 +107,11 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Crosslink-NX VIP Board") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip 0 or 1 (default=none)") - parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") - parser.add_argument("--prog-target", default="direct", help="Programming Target: direct or flash") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip: none (default), 0 or 1") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") + parser.add_argument("--prog-target", default="direct", help="Programming Target: direct (default) or flash") builder_args(parser) soc_core_args(parser) args = parser.parse_args() diff --git a/litex_boards/targets/de0nano.py b/litex_boards/targets/de0nano.py index 8f3d5b8..be92e25 100755 --- a/litex_boards/targets/de0nano.py +++ b/litex_boards/targets/de0nano.py @@ -96,9 +96,9 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE0-Nano") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() diff --git a/litex_boards/targets/de10lite.py b/litex_boards/targets/de10lite.py index 10ff746..1677345 100755 --- a/litex_boards/targets/de10lite.py +++ b/litex_boards/targets/de10lite.py @@ -104,11 +104,11 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Lite") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--with-vga", action="store_true", help="Enable VGA support") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-vga", action="store_true", help="Enable VGA support") args = parser.parse_args() soc = BaseSoC(with_vga=args.with_vga, **soc_sdram_argdict(args)) diff --git a/litex_boards/targets/de10nano.py b/litex_boards/targets/de10nano.py index 2dbd757..781afe3 100755 --- a/litex_boards/targets/de10nano.py +++ b/litex_boards/targets/de10nano.py @@ -115,14 +115,14 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Nano") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - builder_args(parser) - soc_sdram_args(parser) + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board") parser.add_argument("--with-mister-vga", action="store_true", help="Enable VGA with Mister expansion board") - parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate") + parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate") args = parser.parse_args() + builder_args(parser) + soc_sdram_args(parser) soc = BaseSoC( with_mister_sdram = args.with_mister_sdram, with_mister_vga = args.with_mister_vga, diff --git a/litex_boards/targets/ecp5_evn.py b/litex_boards/targets/ecp5_evn.py index f97e600..1d473ef 100755 --- a/litex_boards/targets/ecp5_evn.py +++ b/litex_boards/targets/ecp5_evn.py @@ -68,13 +68,13 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ECP5 Evaluation Board") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond") + parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)") + parser.add_argument("--x5-clk-freq", type=int, help="Use X5 oscillator as system clock at the specified frequency") builder_args(parser) soc_core_args(parser) - parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default=60MHz)") - parser.add_argument("--x5-clk-freq", type=int, help="Use X5 oscillator as system clock at the specified frequency") args = parser.parse_args() soc = BaseSoC(toolchain=args.toolchain, diff --git a/litex_boards/targets/ecpix5.py b/litex_boards/targets/ecpix5.py index 0a21bcb..845246e 100755 --- a/litex_boards/targets/ecpix5.py +++ b/litex_boards/targets/ecpix5.py @@ -125,13 +125,13 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ECPIX-5") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") builder_args(parser) soc_core_args(parser) trellis_args(parser) - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_core_argdict(args)) diff --git a/litex_boards/targets/fk33.py b/litex_boards/targets/fk33.py index c112695..d042e42 100755 --- a/litex_boards/targets/fk33.py +++ b/litex_boards/targets/fk33.py @@ -101,7 +101,7 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on FK33") - parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") parser.add_argument("--load", action="store_true", help="Load bitstream") diff --git a/litex_boards/targets/fomu.py b/litex_boards/targets/fomu.py index 7ebce41..78cc248 100755 --- a/litex_boards/targets/fomu.py +++ b/litex_boards/targets/fomu.py @@ -148,8 +148,8 @@ def flash(bios_flash_offset): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Fomu") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--bios-flash-offset", default=0x60000, help="BIOS offset in SPI Flash") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--bios-flash-offset", default=0x60000, help="BIOS offset in SPI Flash (default: 0x60000)") parser.add_argument("--flash", action="store_true", help="Flash Bitstream") builder_args(parser) soc_core_args(parser) diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py index 002db8b..e03a891 100755 --- a/litex_boards/targets/genesys2.py +++ b/litex_boards/targets/genesys2.py @@ -97,12 +97,12 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") - parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support") args = parser.parse_args() assert not (args.with_ethernet and args.with_etherbone) diff --git a/litex_boards/targets/hadbadge.py b/litex_boards/targets/hadbadge.py index c35ce9d..a0adf9f 100755 --- a/litex_boards/targets/hadbadge.py +++ b/litex_boards/targets/hadbadge.py @@ -86,9 +86,9 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Hackaday Badge") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") - parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency (default=48MHz)") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond") + parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency (default: 48MHz)") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) diff --git a/litex_boards/targets/icebreaker.py b/litex_boards/targets/icebreaker.py index 806f27a..068cd89 100755 --- a/litex_boards/targets/icebreaker.py +++ b/litex_boards/targets/icebreaker.py @@ -125,7 +125,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash") + parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash (default: 0x40000)") parser.add_argument("--flash", action="store_true", help="Flash Bitstream") builder_args(parser) soc_core_args(parser) diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py index ad5a21c..e6aeec8 100755 --- a/litex_boards/targets/kc705.py +++ b/litex_boards/targets/kc705.py @@ -132,12 +132,12 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on KC705") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - builder_args(parser) - soc_sdram_args(parser) + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over SFP2SATA)") + builder_args(parser) + soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, with_sata=args.with_sata, **soc_sdram_argdict(args)) diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py index c57951f..42c60e3 100755 --- a/litex_boards/targets/linsn_rv901t.py +++ b/litex_boards/targets/linsn_rv901t.py @@ -120,12 +120,12 @@ class EthernetSoC(BaseSoC): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Linsn RV901T") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") - parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)") args = parser.parse_args() if args.with_ethernet: diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py index b35624d..ae99d76 100755 --- a/litex_boards/targets/logicbone.py +++ b/litex_boards/targets/logicbone.py @@ -159,17 +159,17 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Logicbone") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") + parser.add_argument("--device", default="45F", help="FPGA device: (default: 45F)") + parser.add_argument("--sdram-device", default="MT41K512M16", help="SDRAM device (default: MT41K512M16)") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) - parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") - parser.add_argument("--device", default="45F", help="ECP5 device (default=45F)") - parser.add_argument("--sdram-device", default="MT41K512M16", help="ECP5 device (default=MT41K512M16)") - parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") - parser.add_argument("--with-sdcard", action="store_true", help="enable SDCard support") args = parser.parse_args() soc = BaseSoC( diff --git a/litex_boards/targets/mimas_a7.py b/litex_boards/targets/mimas_a7.py index d7c7ea8..339a447 100755 --- a/litex_boards/targets/mimas_a7.py +++ b/litex_boards/targets/mimas_a7.py @@ -98,12 +98,12 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Mimas A7") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") builder_args(parser) soc_sdram_args(parser) vivado_build_args(parser) - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) diff --git a/litex_boards/targets/minispartan6.py b/litex_boards/targets/minispartan6.py index 69372c6..4b5d4cd 100755 --- a/litex_boards/targets/minispartan6.py +++ b/litex_boards/targets/minispartan6.py @@ -99,9 +99,9 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() diff --git a/litex_boards/targets/mist.py b/litex_boards/targets/mist.py index ae1a8d2..be01cd0 100755 --- a/litex_boards/targets/mist.py +++ b/litex_boards/targets/mist.py @@ -104,11 +104,11 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on MIST") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--with-vga", action="store_true", help="Enable VGA support") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-vga", action="store_true", help="Enable VGA support") args = parser.parse_args() soc = BaseSoC(with_vga=args.with_vga, **soc_sdram_argdict(args)) diff --git a/litex_boards/targets/netv2.py b/litex_boards/targets/netv2.py index 0196fb2..501e61e 100755 --- a/litex_boards/targets/netv2.py +++ b/litex_boards/targets/netv2.py @@ -100,11 +100,11 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr.py index d72b766..8ec21a4 100755 --- a/litex_boards/targets/nexys4ddr.py +++ b/litex_boards/targets/nexys4ddr.py @@ -98,14 +98,14 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Nexys4DDR") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") + parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") - parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") - parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") args = parser.parse_args() soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), diff --git a/litex_boards/targets/nexys_video.py b/litex_boards/targets/nexys_video.py index 17b7bb7..e769d62 100755 --- a/litex_boards/targets/nexys_video.py +++ b/litex_boards/targets/nexys_video.py @@ -128,14 +128,14 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Nexys Video") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - builder_args(parser) - soc_sdram_args(parser) + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over FMCRAID)") + builder_args(parser) + soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, with_sata=args.with_sata, **soc_sdram_argdict(args)) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 5bbe14a..3e684a0 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -32,8 +32,8 @@ from litedram.phy import ECP5DDRPHY class _CRG(Module): def __init__(self, platform, sys_clk_freq, with_usb_pll=False): self.rst = Signal() - self.clock_domains.cd_por = ClockDomain(reset_less=True) - self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_por = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() # # # @@ -208,17 +208,17 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--toolchain", default="trellis", help="FPGA use, trellis (default) or diamond") + parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency (default: 48MHz)") + parser.add_argument("--revision", default="0.2", help="Board Revision: 0.1 or 0.2 (default)") + parser.add_argument("--device", default="25F", help="ECP5 device (default: 25F)") + parser.add_argument("--sdram-device", default="MT41K64M16", help="ECP5 device (default: MT41K64M16)") + parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) - parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency (default=48MHz)") - parser.add_argument("--revision", default="0.2", help="Board Revision {0.1, 0.2} (default=0.2)") - parser.add_argument("--device", default="25F", help="ECP5 device (default=25F)") - parser.add_argument("--sdram-device", default="MT41K64M16", help="ECP5 device (default=MT41K64M16)") - parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") args = parser.parse_args() soc = BaseSoC( diff --git a/litex_boards/targets/pano_logic_g2.py b/litex_boards/targets/pano_logic_g2.py index 0d4d426..ebda64f 100755 --- a/litex_boards/targets/pano_logic_g2.py +++ b/litex_boards/targets/pano_logic_g2.py @@ -80,13 +80,13 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Pano Logic G2") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--revision", default="c", help="Board revision c (default) or b") - builder_args(parser) - soc_core_args(parser) + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--revision", default="c", help="Board revision c (default) or b") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") + builder_args(parser) + soc_core_args(parser) args = parser.parse_args() assert not (args.with_ethernet and args.with_etherbone) diff --git a/litex_boards/targets/simple.py b/litex_boards/targets/simple.py index b09a52c..29eea19 100755 --- a/litex_boards/targets/simple.py +++ b/litex_boards/targets/simple.py @@ -48,12 +48,12 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="Generic LiteX SoC") - parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("platform", help="Module name of the platform to build for") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--toolchain", default=None, help="FPGA toolchain (None default)") builder_args(parser) soc_core_args(parser) - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") - parser.add_argument("platform", help="Module name of the platform to build for") - parser.add_argument("--toolchain", default=None, help="FPGA gateware toolchain used for build") args = parser.parse_args() platform_module = importlib.import_module(args.platform) diff --git a/litex_boards/targets/tec0117.py b/litex_boards/targets/tec0117.py index 73bb250..56d9b42 100755 --- a/litex_boards/targets/tec0117.py +++ b/litex_boards/targets/tec0117.py @@ -105,8 +105,8 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--bios-flash-offset", default=0, help="BIOS offset in SPI Flash") - parser.add_argument("--flash", action="store_true", help="Flash bios") + parser.add_argument("--bios-flash-offset", default=0x00000, help="BIOS offset in SPI Flash (0x00000 default)") + parser.add_argument("--flash", action="store_true", help="Flash BIOS") builder_args(parser) soc_core_args(parser) args = parser.parse_args() diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index 807e57d..3d14055 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -160,16 +160,16 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Trellis Board") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") + parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) - parser.add_argument("--sys-clk-freq", default=75e6, help="system clock frequency (default=75MHz)") - parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") - parser.add_argument("--with-spi-sdcard", action="store_true", help="enable SPI-mode SDCard support") - parser.add_argument("--with-sdcard", action="store_true", help="enable SDCard support") args = parser.parse_args() soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py index 1adc9e0..2a243ca 100755 --- a/litex_boards/targets/ulx3s.py +++ b/litex_boards/targets/ulx3s.py @@ -129,17 +129,17 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") - parser.add_argument("--device", dest="device", default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F") - parser.add_argument("--revision", default="2.0", type=str, help="Board revision 2.0 (default), 1.7") - parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default=50MHz)") - parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)") - parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") - parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") - parser.add_argument("--with-oled", action="store_true", help="Enable SDD1331 OLED support") - parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond") + parser.add_argument("--device", default="LFE5U-45F", help="FPGA device: LFE5U-12F, LFE5U-25F, LFE5U-45F (default) or LFE5U-85F") + parser.add_argument("--revision", default="2.0", help="Board revision: 2.0 (default) or 1.7") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") + parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16 (default), AS4C32M16 or AS4C16M16") + parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") + parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") + parser.add_argument("--with-oled", action="store_true", help="Enable SDD1331 OLED support") + parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index a4d134a..cd37590 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -134,17 +134,17 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") + parser.add_argument("--device", default="LFE5UM5G", help="FPGA device (LFE5UM5G (default) or LFE5UM)") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") + parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) - parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") - parser.add_argument("--device", default="LFE5UM5G", help="ECP5 device (LFE5UM5G (default) or LFE5UM)") - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") - parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") - parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)") args = parser.parse_args() assert not (args.with_ethernet and args.with_etherbone) diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py index 014b131..3263b69 100755 --- a/litex_boards/targets/xcu1525.py +++ b/litex_boards/targets/xcu1525.py @@ -141,10 +141,10 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on XCU1525") parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--ddram-channel", default="0", help="DDRAM channel") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--ddram-channel", default="0", help="DDRAM channel (default: 0)") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") - parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args()