From bd20b31a5c9241933647c30cc54f0f45a0e541f3 Mon Sep 17 00:00:00 2001 From: inc <87362+inc@users.noreply.github.com> Date: Tue, 21 Feb 2023 11:18:22 +0100 Subject: [PATCH 1/2] add support for machdyne kopflos board --- README.md | 1 + litex_boards/platforms/machdyne_kopflos.py | 159 +++++++++++++++ litex_boards/targets/machdyne_kopflos.py | 221 +++++++++++++++++++++ 3 files changed, 381 insertions(+) create mode 100644 litex_boards/platforms/machdyne_kopflos.py create mode 100755 litex_boards/targets/machdyne_kopflos.py diff --git a/README.md b/README.md index 390e84e..7f13c18 100644 --- a/README.md +++ b/README.md @@ -171,6 +171,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try! ├── machdyne_krote ├── machdyne_noir ├── machdyne_schoko + ├── machdyne_kopflos ├── marblemini ├── marble ├── micronova_mercury2 diff --git a/litex_boards/platforms/machdyne_kopflos.py b/litex_boards/platforms/machdyne_kopflos.py new file mode 100644 index 0000000..859d744 --- /dev/null +++ b/litex_boards/platforms/machdyne_kopflos.py @@ -0,0 +1,159 @@ +# +# This file is part of LiteX-Boards. +# +# Copright (c) 2023 Lone Dynamics Corporation +# +# SPDX-License-Identifier: BSD-2-Clause + +from litex.build.generic_platform import * +from litex.build.lattice import LatticePlatform +from litex.build.openfpgaloader import OpenFPGALoader + +# IOs ---------------------------------------------------------------------------------------------- + +_io_vx = [ + + # Clock + ("clk48", 0, Pins("A7"), IOStandard("LVCMOS33")), + + # Leds + ("user_led", 0, Pins("C1"), IOStandard("LVCMOS33")), + ("user_led", 1, Pins("E1"), IOStandard("LVCMOS33")), + ("user_led", 2, Pins("G1"), IOStandard("LVCMOS33")), + ("rgb_led", 0, + Subsignal("r", Pins("C1"), IOStandard("LVCMOS33")), + Subsignal("g", Pins("E1"), IOStandard("LVCMOS33")), + Subsignal("b", Pins("G1"), IOStandard("LVCMOS33")), + ), + + # Buttons + ("user_btn", 0, Pins("C2"), IOStandard("LVCMOS33")), + + # DDR3L + ("ddram", 0, + Subsignal("a", Pins( + "R15 L13 P14 R14 L12 T14 N11 T13", + "P12 T15 C14 M13 E14 R13 M14 D14"), + IOStandard("SSTL135_I")), + Subsignal("ba", Pins("N16 K13 P16"), IOStandard("SSTL135_I")), + Subsignal("ras_n", Pins("L16"), IOStandard("SSTL135_I")), + Subsignal("cas_n", Pins("M16"), IOStandard("SSTL135_I")), + Subsignal("we_n", Pins("P15"), IOStandard("SSTL135_I")), + Subsignal("cs_n", Pins("M15"), IOStandard("SSTL135_I")), + Subsignal("dm", Pins("F13 J13"), IOStandard("SSTL135_I")), + Subsignal("dq", Pins( + "F14 E16 F12 F15 G13 B16 G12 B15", + "J14 J16 K15 K14 H14 K16 H13 J15"), + IOStandard("SSTL135_I"), + Misc("TERMINATION=75")), + Subsignal("dqs_p", Pins("D16 G16"), IOStandard("SSTL135D_I"), + Misc("TERMINATION=OFF DIFFRESISTOR=100")), + Subsignal("clk_p", Pins("C16"), IOStandard("SSTL135D_I")), + Subsignal("cke", Pins("K12"), IOStandard("SSTL135_I")), + Subsignal("odt", Pins("L15"), IOStandard("SSTL135_I")), + Subsignal("reset_n", Pins("R12"), IOStandard("SSTL135_I")), + Misc("SLEWRATE=FAST") + ), + + # USB-C + ("usb", 0, + Subsignal("d_p", Pins("T6")), + Subsignal("d_n", Pins("R6")), + Subsignal("pullup", Pins("R7")), + IOStandard("LVCMOS33") + ), + + # DUAL USB HOST + ("usb_host", 0, + Subsignal("dp", Pins("R4 P1")), + Subsignal("dm", Pins("T3 R1")), + IOStandard("LVCMOS33") + ), + + # ETHERNET + ("eth_clocks", 0, + Subsignal("ref_clk", Pins("M1")), + IOStandard("LVCMOS33") + ), + ("eth", 0, + Subsignal("rx_data", Pins("N1 P2")), + Subsignal("tx_data", Pins("T2 R2")), + Subsignal("tx_en", Pins("P3")), + Subsignal("crs_dv", Pins("M3")), + Subsignal("rst_n", Pins("N4")), + IOStandard("LVCMOS33") + ), + + # DEBUG UART + ("serial", 0, + Subsignal("tx", Pins("B1")), + Subsignal("rx", Pins("B2")), + IOStandard("LVCMOS33") + ), + + # SPI + ("spiflash", 0, + Subsignal("cs_n", Pins("N8")), + Subsignal("miso", Pins("T7")), + Subsignal("mosi", Pins("T8")), + Misc("SLEWRATE=FAST"), + IOStandard("LVCMOS33"), + ), + +] + +_io_v0 = [ + + # SD card w/ SD-mode interface + ("sdcard", 0, + Subsignal("cd", Pins("A5")), + Subsignal("clk", Pins("B4")), + Subsignal("cmd", Pins("A3"), Misc("PULLMODE=UP")), + Subsignal("data", Pins("A4 B5 A2 B3"), Misc("PULLMODE=UP")), + Misc("SLEWRATE=FAST"), + IOStandard("LVCMOS33") + ), + + # SD card w/ SPI interface + ("spisdcard", 0, + Subsignal("clk", Pins("B4")), + Subsignal("mosi", Pins("A3")), + Subsignal("cs_n", Pins("B3")), + Subsignal("miso", Pins("A4")), + Misc("SLEWRATE=FAST"), + IOStandard("LVCMOS33"), + ), + +] + +# Connectors --------------------------------------------------------------------------------------- + +_connectors_vx = [ + ("PMODA", "K3 J2 J3 F1 K2 K1 J1 G2"), + ("PMODB", "N5 M5 T4 P4 N6 M6 R5 P5"), +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(LatticePlatform): + default_clk_name = "clk48" + default_clk_period = 1e9/48e6 + + def __init__(self, revision="v0", device="12F", toolchain="trellis", **kwargs): + assert revision in ["v0"] + assert device in ["12F", "25F", "45F", "85F"] + self.revision = revision + + io = _io_vx + connectors = _connectors_vx + + if revision == "v0": io += _io_v0 + + LatticePlatform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs) + + def create_programmer(self, cable): + return OpenFPGALoader(cable=cable) + + def do_finalize(self, fragment): + LatticePlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6) diff --git a/litex_boards/targets/machdyne_kopflos.py b/litex_boards/targets/machdyne_kopflos.py new file mode 100755 index 0000000..457371c --- /dev/null +++ b/litex_boards/targets/machdyne_kopflos.py @@ -0,0 +1,221 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# Copyright (c) Greg Davill +# Copyright (c) Lone Dynamics Corporation +# +# SPDX-License-Identifier: BSD-2-Clause +# + +import os +import sys +import json + +from migen import * +from litex_boards.platforms import machdyne_kopflos + +from litex.build.lattice.trellis import trellis_args, trellis_argdict +from litex.build.io import DDROutput + +from migen.genlib.resetsync import AsyncResetSynchronizer + +from litex.soc.cores.clock import * +from litex.soc.cores.led import LedChaser +from litex.soc.cores.usb_ohci import USBOHCI + +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * +from litex.soc.interconnect.csr_eventmanager import * + +from litedram.modules import MT41K64M16, MT41K128M16, MT41K256M16, MT41K512M16 +from litedram.phy import ECP5DDRPHY + +from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY + +from litex.soc.integration.soc import SoCRegion + +# CRG --------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq, sdram_rate): + self.rst = Signal() + self.clock_domains.cd_por = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x_i = ClockDomain() + self.clock_domains.cd_init = ClockDomain() + + self.stop = Signal() + self.reset = Signal() + + # Clk / Rst + clk48 = platform.request("clk48") + + # Power on reset + por_count = Signal(16, reset=2**16-1) + por_done = Signal() + self.comb += self.cd_por.clk.eq(clk48) + self.comb += por_done.eq(por_count == 0) + self.sync.por += If(~por_done, por_count.eq(por_count - 1)) + + # PLL + sys2x_clk_ecsout = Signal() + self.submodules.pll = pll = ECP5PLL() + self.comb += pll.reset.eq(~por_done | self.rst) + pll.register_clkin(clk48, 48e6) + pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) + pll.create_clkout(self.cd_init, 24e6) + self.specials += [ + Instance("ECLKBRIDGECS", + i_CLK0 = self.cd_sys2x_i.clk, + i_SEL = 0, + o_ECSOUT = sys2x_clk_ecsout), + Instance("ECLKSYNCB", + i_ECLKI = sys2x_clk_ecsout, + i_STOP = self.stop, + o_ECLKO = self.cd_sys2x.clk), + Instance("CLKDIVF", + p_DIV = "2.0", + i_ALIGNWD = 0, + i_CLKI = self.cd_sys2x.clk, + i_RST = self.reset, + o_CDIVX = self.cd_sys.clk), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), + ] + + pll2 = ECP5PLL() + self.submodules.pll2 = pll2 + pll2.register_clkin(clk48, 48e6) + + self.clock_domains.cd_usb_12 = ClockDomain() + self.clock_domains.cd_usb = ClockDomain() + self.clock_domains.cd_usb_48 = ClockDomain() + self.cd_usb_48 = self.cd_usb + pll2.create_clkout(self.cd_usb, 48e6) + pll2.create_clkout(self.cd_usb_12, 12e6) + self.comb += pll2.reset.eq(~por_done) + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + mem_map = {**SoCCore.mem_map, **{ + "usb_ohci": 0xc0000000, + }} + def __init__(self, revision="v0", device="12F", sdram_device="MT41K128M16", sdram_rate="1:2", sys_clk_freq=int(50e6), toolchain="trellis", with_led_chaser=True, with_usb_host=False, with_ethernet=False, **kwargs): + + platform = machdyne_kopflos.Platform(revision=revision, device=device ,toolchain=toolchain) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate) + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Schoko", **kwargs) + + # DDR3L ---------------------------------------------------------------------------------- + + if not self.integrated_main_ram_size: + available_sdram_modules = { + "MT41K64M16": MT41K64M16, + "MT41K128M16": MT41K128M16, + "MT41K256M16": MT41K256M16, + "MT41K512M16": MT41K512M16, + } + sdram_module = available_sdram_modules.get(sdram_device) + + ddram_pads = platform.request("ddram") + self.submodules.ddrphy = ECP5DDRPHY( + pads = ddram_pads, + sys_clk_freq = sys_clk_freq, + cmd_delay = 0 if sys_clk_freq > 64e6 else 100) + self.ddrphy.settings.rtt_nom = "disabled" + self.comb += self.crg.stop.eq(self.ddrphy.init.stop) + self.comb += self.crg.reset.eq(self.ddrphy.init.reset) + self.add_sdram("sdram", + phy = self.ddrphy, + module = sdram_module(sys_clk_freq, "1:2"), + l2_cache_size = kwargs.get("l2_size", 8192) + ) + + # USB Host --------------------------------------------------------------------------------- + if with_usb_host: + self.submodules.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6)) + self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False)) + self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma) + self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt) + + if with_ethernet: + from liteeth.phy.rmii import LiteEthPHYRMII + self.submodules.ethphy = LiteEthPHYRMII( + clock_pads = platform.request("eth_clocks"), + pads = platform.request("eth"), + with_hw_init_reset=True, + hw_init_mode_cfg=[1,1,1], + refclk_cd=None) + self.add_ethernet(phy=self.ethphy) + + # Leds ------------------------------------------------------------------------------------- + if with_led_chaser: + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + +# Build -------------------------------------------------------------------------------------------- + +def main(): + from litex.soc.integration.soc import LiteXSoCArgumentParser + parser = LiteXSoCArgumentParser(description="LiteX SoC on Schoko") + target_group = parser.add_argument_group(title="Target options") + target_group.add_argument("--build", action="store_true", help="Build design.") + target_group.add_argument("--load", action="store_true", help="Load bitstream to SRAM.") + target_group.add_argument("--flash", action="store_true", help="Flash bitstream to MMOD.") + target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).") + target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") + target_group.add_argument("--revision", default="v0", help="Board Revision (v0).") + target_group.add_argument("--device", default="12F", help="ECP5 device (12F, 25F, 45F or 85F).") + target_group.add_argument("--cable", default="usb-blaster", help="Specify an openFPGALoader cable.") + target_group.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.") + target_group.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.") + target_group.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.") + target_group.add_argument("--with-ethernet", action="store_true", help="Enable ethernet support.") + target_group.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.") + target_group.add_argument("--sdram-device", default="MT41K128M16", help="SDRAM device.") + + builder_args(parser) + soc_core_args(parser) + trellis_args(parser) + args = parser.parse_args() + + soc = BaseSoC( + toolchain = args.toolchain, + revision = args.revision, + device = args.device, + sys_clk_freq = int(float(args.sys_clk_freq)), + sdram_device = args.sdram_device, + with_usb_host = args.with_usb_host, + with_ethernet = args.with_ethernet, + **soc_core_argdict(args)) + + if args.with_sdcard: + soc.add_sdcard() + + if args.with_spi_sdcard: + soc.add_spi_sdcard() + + builder = Builder(soc, **builder_argdict(args)) + builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} + + if args.build: + builder.build(**builder_kargs) + + if args.load: + prog = soc.platform.create_programmer(args.cable) + prog.load_bitstream(builder.get_bitstream_filename(mode="sram")) + + if args.flash: + prog = soc.platform.create_programmer(args.cable) + prog.flash(0x100000, builder.get_bitstream_filename(mode="sram")) + +if __name__ == "__main__": + main() From 33cfe59614905002ef3a098f02e6d45249cfe541 Mon Sep 17 00:00:00 2001 From: inc <87362+inc@users.noreply.github.com> Date: Wed, 22 Feb 2023 08:00:58 +0100 Subject: [PATCH 2/2] add pullups for kopflos ethernet --- litex_boards/platforms/machdyne_kopflos.py | 4 ++-- litex_boards/targets/machdyne_kopflos.py | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/litex_boards/platforms/machdyne_kopflos.py b/litex_boards/platforms/machdyne_kopflos.py index 859d744..541cdfa 100644 --- a/litex_boards/platforms/machdyne_kopflos.py +++ b/litex_boards/platforms/machdyne_kopflos.py @@ -76,10 +76,10 @@ _io_vx = [ IOStandard("LVCMOS33") ), ("eth", 0, - Subsignal("rx_data", Pins("N1 P2")), + Subsignal("rx_data", Pins("N1 P2"), Misc("PULLMODE=UP")), Subsignal("tx_data", Pins("T2 R2")), Subsignal("tx_en", Pins("P3")), - Subsignal("crs_dv", Pins("M3")), + Subsignal("crs_dv", Pins("M3"), Misc("PULLMODE=UP")), Subsignal("rst_n", Pins("N4")), IOStandard("LVCMOS33") ), diff --git a/litex_boards/targets/machdyne_kopflos.py b/litex_boards/targets/machdyne_kopflos.py index 457371c..f37c53e 100755 --- a/litex_boards/targets/machdyne_kopflos.py +++ b/litex_boards/targets/machdyne_kopflos.py @@ -151,7 +151,6 @@ class BaseSoC(SoCCore): clock_pads = platform.request("eth_clocks"), pads = platform.request("eth"), with_hw_init_reset=True, - hw_init_mode_cfg=[1,1,1], refclk_cd=None) self.add_ethernet(phy=self.ethphy)